13.19 Power Management Control and Status Register

The power management control and status register implements the control and status of the Smart Card controller. This register is not affected by the internally generated reset caused by the transition from the D3hot to D0 state. See Table 13−12 for a complete description of the register contents.

Bit

15

 

14

13

 

12

 

 

 

11

10

9

8

7

 

6

 

5

4

3

 

 

2

 

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

 

 

Power management control and status

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RCU

 

R

R

 

R

 

 

 

 

R

R

R

RW

 

R

 

R

 

R

R

 

R

 

R

 

RW

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

0

 

0

 

 

 

0

0

0

0

0

 

0

 

0

0

0

 

 

0

 

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

Power management control and status

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

48h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read/Clear/Update, Read/Write, Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

0000h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 13−12. Power Management Control and Status Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

 

FIELD NAME

 

TYPE

 

 

 

 

 

 

 

 

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15 ‡

 

PME_STAT

 

RCU

 

 

 

 

 

 

status. This bit is set when the function would normally assert the

 

signal independent of the

 

 

 

 

 

PME

 

PME

 

 

 

 

 

 

 

 

 

 

state of PME_EN bit. Writing a 1 to this bit clears it and causes the function to stop asserting a PME

 

 

 

 

 

 

 

 

 

 

(if enabled). Writing a 0 has no effect. This bit is initialized by GRST only when the PME_D3cold bit

 

 

 

 

 

 

 

 

 

 

is 1.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14−9

 

RSVD

 

R

 

 

Reserved. Bits 14−9 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8 ‡

 

PME_EN

 

RW

 

 

 

 

 

 

enable. This bit is initialized by

 

 

only when PME_D3cold bit is 1.

 

 

 

 

 

 

 

 

PME

GRST

 

 

 

 

7−2

 

RSVD

 

R

 

 

Reserved. Bits 7−2 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1−0 ‡

 

DSTATE

 

RW

 

 

Device State: This bit field controls device power management state. Invalid state assignments are

 

 

 

 

 

 

 

 

 

 

ignored. (ex. Current state 10b writing 01b. This is rejected and stays 10b. See the latest PCI Local

 

 

 

 

 

 

 

 

 

 

Bus Specification.) This bit field is initialized by GRST only when PME_D3cold bit is 1.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

One or more bits in this register are cleared only by the assertion of GRST.

13.20 Power Management Bridge Support Extension Register

The power management bridge support extension register provides extended power-management features not applicable to the Smart Card controller; thus, it is read-only and returns 0 when read.

Bit

 

7

6

5

4

3

2

 

1

0

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

Power management bridge support extension

 

 

 

 

 

 

 

 

 

 

 

 

Type

 

R

R

R

R

R

R

 

R

R

 

 

 

 

 

 

 

 

 

 

 

Default

 

0

0

0

0

0

0

 

0

0

 

 

 

 

 

 

 

 

 

 

 

Register:

Power management bridge support extension

 

Offset:

4Ah

 

 

 

 

 

 

 

 

Type:

Read-only

 

 

 

 

 

 

 

Default:

00h

 

 

 

 

 

 

 

13−12

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Texas Instruments PCI7411, PCI7611, PCI7621, PCI7421 manual PME Grst Rsvd, Dstate, 13−12