Texas Instruments PCI7621, PCI7411, PCI7611 14. CardBus PC Card Interface Control Terminals, BCCD2

Table 2−14. CardBus PC Card Interface Control Terminals

If any CardBus PC Card interface control terminal is unused, then the terminal may be left floating.

SKT A TERMINAL

SKT B TERMINAL†

DESCRIPTION

I/O

INPUT

OUTPUT

PU/

POWER

NAME

NO.

NAME

NO.

TYPE

PD

RAIL

CardBus audio. CAUDIO is a digital input signal from

A_CAUDIO

A02

B_CAUDIO

C17

a PC Card to the system speaker. The controller

I

PCII4

PCIO4

PU3

VCCA/

supports the binary audio mode and outputs a binary

VCCB

signal from the card to SPKROUT.

CardBus lock.

is used to gain exclusive

VCCA/

E10

J19

CBLOCK

I/O

PCII4

PCIO4

PU3

A_CBLOCK

B_CBLOCK

access to a target.

VCCB

CardBus detect 1 and CardBus detect 2.

and

CCD1

A_CCD1

C15

B_CCD1

N13

CCD2 are used in conjunction with CVS1 and CVS2

I

TTLI2

PU4

A_CCD2

E05

B_CCD2

B17

to identify card insertion and interrogate cards to

determine the operating voltage and card type.

CardBus device select. The controller asserts

CDEVSEL to claim a CardBus cycle as the target

C09

H19

device. As a CardBus initiator on the bus, the

I/O

PCII4

PCIO4

PU3

VCCA/

A_CDEVSEL

B_CDEVSEL

controller monitors CDEVSEL until a target responds.

VCCB

If no target responds before timeout occurs, then the

controller terminates the cycle with an initiator abort.

CardBus cycle frame.

is driven by the

CFRAME

initiator of a CardBus bus cycle. CFRAME is asserted

C08

G19

to indicate that a bus transaction is beginning, and

I/O

PCII7

PCIO7

VCCA/

A_CFRAME

B_CFRAME

data transfers continue while this signal is asserted.

VCCB

When CFRAME is deasserted, the CardBus bus

transaction is in the final data phase.

CardBus bus grant.

is driven by the controller

CGNT

B09

J15

to grant a CardBus PC Card access to the CardBus

O

PCII7

PCIO7

VCCA/

A_CGNT

B_CGNT

bus after the current data transaction has been

VCCB

completed.

CardBus interrupt.

is asserted low by a CardBus

VCCA/

C04

B19

CINT

I

PCII4

PCIO4

PU3

A_CINT

B_CINT

PC Card to request interrupt servicing from the host.

VCCB

CardBus initiator ready.

indicates the ability of

CIRDY

the CardBus initiator to complete the current data

B08

J13

phase of the transaction. A data phase is completed

I/O

PCII4

PCIO4

PU3

VCCA/

A_CIRDY

B_CIRDY

on a rising edge of CCLK when both CIRDY and

VCCB

CTRDY are asserted. Until CIRDY and CTRDY are

both sampled asserted, wait states are inserted.

CardBus parity error.

reports parity errors

CPERR

F10

J18

during CardBus transactions, except during special

I/O

PCII4

PCIO4

PU3

VCCA/

A_CPERR

B_CPERR

cycles. It is driven low by a target two clocks following

VCCB

the data cycle during which a parity error is detected.

CardBus request.

indicates to the arbiter that

CREQ

VCCA/

A_CREQ

E07

B_CREQ

E18

the CardBus PC Card desires use of the CardBus bus

I

PCII4

PCIO4

PU3

VCCB

as an initiator.

CardBus system error.

reports address parity

CSERR

errors and other system errors that could lead to

catastrophic results. CSERR is driven by the card

VCCA/

A_CSERR

B03

B_CSERR

B18

synchronous to CCLK, but deasserted by a weak

I

PCII4

PCIO4

PU3

VCCB

pullup; deassertion may take several CCLK periods.

The controller can report CSERR to the system by

assertion of SERR on the PCI interface.

†These terminals are reserved for the PCI7611 and PCI7411 controllers.

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