Texas Instruments PCI7621, PCI7411, PCI7611, PCI7421 manual Socket Event Register, Socket event

6.1 Socket Event Register

This register indicates a change in socket status has occurred. These bits do not indicate what the change is, only that one has occurred. Software must read the socket present state register for current status. Each bit in this register can be cleared by writing a 1 to that bit. The bits in this register can be set to a 1 by software through writing a 1 to the corresponding bit in the socket force event register. All bits in this register are cleared by PCI reset. They can be immediately set again, if, when coming out of PC Card reset, the bridge finds the status unchanged (i.e., CSTSCHG reasserted or card detect is still true). Software needs to clear this register before enabling interrupts. If it is not cleared and interrupts are enabled, then an unmasked interrupt is generated based on any bit that is set. See Table 6−2 for a complete description of the register contents.

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Name								Socket event
Type	R	R	R	R	R	R	R	R	R	R	R	R	R	R	R	R
Default	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Socket event

Type

R

R

R

R

R

R

R

R

R

R

R

R

RWC

RWC

RWC

RWC

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Register:

Socket event

Offset:

CardBus Socket Address + 00h

Type:

Read-only, Read/Write to Clear

Default:

0000 0000h

Table 6−2. Socket Event Register Description

BIT

SIGNAL

TYPE

FUNCTION

31−4

RSVD

R

These bits return 0s when read.

3†

PWREVENT

RWC

Power cycle. This bit is set when the PCI7x21/PCI7x11 controller detects that the PWRCYCLE bit in the

socket present state register (offset 08h, see Section 6.3) has changed. This bit is cleared by writing a 1.

2†

CD2EVENT

RWC

CCD2.

This bit is set when the PCI7x21/PCI7x11 controller detects that the CDETECT2 field in the socket

present state register (offset 08h, see Section 6.3) has changed. This bit is cleared by writing a 1.

1†

CD1EVENT

RWC

CCD1.

This bit is set when the PCI7x21/PCI7x11 controller detects that the CDETECT1 field in the socket

present state register (offset 08h, see Section 6.3) has changed. This bit is cleared by writing a 1.

CSTSCHG. This bit is set when the CARDSTS field in the socket present state register (offset 08h, see

0†

CSTSEVENT

RWC

Section 6.3) has changed state. For CardBus cards, this bit is set on the rising edge of the CSTSCHG

signal. For 16-bit PC Cards, this bit is set on both transitions of the CSTSCHG signal. This bit is reset by

writing a 1.

†This bit is cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or GRST.

6−2