Texas Instruments PCI7411, PCI7611, PCI7621, PCI7421 15. Ieee 1394 Physical Layer Terminals, 26

Table 2−15. IEEE 1394 Physical Layer Terminals

TERMINAL		DESCRIPTION	I/O	INPUT	OUTPUT	EXTERNAL	PIN STRAPPING
NAME	NO.		TYPE			COMPONENTS	(IF USED)
		Cable not active. This terminal is asserted high when there
		are no ports receiving incoming bias voltage. If it is not used,
		then this terminal must be strapped either to DVDD or GND
		through a resistor. The CNA terminal can be disabled by
CNA	P15	setting bit 7 (CNAOUT) of the PCI PHY control register at	I/O		LVCO1		Tie to GND
		offset ECh in the PCI configuration space (see Section 7.22,
		PCI PHY Control Register). This bit is loaded by the serial
		EEPROM. If an EEPROM is implemented and CNA
		functionality is needed, then the appropriate bit in the serial
		EEPROM must be cleared as defined in Table 3−9.
		Cable power status input. This terminal is normally				390-kΩseries
						resistor to
		connected to cable power through a 400-kΩresistor. This					Pullup to VCC
						BUSPOWER if
CPS	M11	circuit drives an internal comparator that is used to detect	FT	FT			through 1-kΩ
						providing power
		the presence of cable power. If CPS is not used to detect					resistor
						through the 1394
		cable power, then this terminal must be pulled to GND.
						port
PC0	R12	Power class programming inputs. On hardware reset, these				Pullup resistors if
		inputs set the default value of the power class indicated				high. Can be tied
PC1	U13		I	LVCI1			Tie to GND
		during self-ID. Programming is done by tying these terminals				directly to ground
PC2	V13
		high or low.				if set to low.
		Current-setting resistor terminals. These terminals are				6.34-kΩ ±1%
		connected to an external resistance to set the internal					Float
R0	U18					resistor between
		operating currents and cable driver output currents. A	—				Pull directly to
R1	U19					R0 and R1 per
		resistance of 6.34 kΩ ±1% is required to meet the IEEE Std					VCC
						1394 specification
		1394-1995 output voltage limits.
TPA0P	V15	Twisted-pair cable A differential signal terminals. Board trace				1394 termination
			I/O			(see reference	Float
TPA0N	W15
		lengths from each pair of positive and negative differential
						schematics)
		signal pins must be matched and as short as possible to the
						1394 termination
TPA1P	V18	external load resistors and to the cable connector. For an
			I/O			(see reference	Float
TPA1N	W18	unused port, TPA+ and TPA− can be left open.
						schematics)
		Twisted-pair bias output. This provides the 1.86-V nominal
		bias voltage needed for proper operation of the twisted-pair				1394 termination
TPBIAS0	U15	cable drivers and receivers and for signaling to the remote
			I/O			(see reference	Float
TPBIAS1	U17	nodes that there is an active cable connection. Each of
						schematics)
		these pins must be decoupled with a 1.0-∝F capacitor to
		ground.
TPB0P	V14	Twisted-pair cable B differential signal terminals. Board trace				1394 termination
			I/O			(see reference	Tie to GND
TPB0N	W14
		lengths from each pair of positive and negative differential
						schematics)
		signal pins must be matched and as short as possible to the
						1394 termination
TPB1P	V16	external load resistors and to the cable connector. For an
			I/O			(see reference	Tie to GND
TPB1N	W16	unused port, TPB+ and TPB− must be pulled to ground.
						schematics)
		Crystal oscillator inputs. These pins connect to a
		24.576-MHz parallel resonant fundamental mode crystal.
		The optimum values for the external shunt capacitors are
		dependent on the specifications of the crystal used (see				24.576-MHz
XI	R18	Section 3.9.2, Crystal Selection). An external clock input can	—			oscillator (see	Tie to GND
XO	R19	be connected to the XI terminal. When using an external				implementation	Float
		clock input, the XO terminal must be left unconnected, and				guide)
		the clock must be supplied before the controller is taken out
		of reset. Refer to Section 3.9.2 for the operating
		characteristics of the XI terminal.

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