Texas Instruments PCI7621 3. Page 0 Port Status Register Configuration, BIT Position Address

10.2 Port Status Register

The port status page provides access to configuration and status information for each of the ports. The port is selected by writing 0 to the Page_Select field and the desired port number to the Port_Select field in base register 7. Table 10−3 shows the configuration of the port status page registers and Table 10−4 shows the corresponding field descriptions. If the selected port is not implemented, all registers in the port status page are read as 0.

Table 10−3. Page 0 (Port Status) Register Configuration

						BIT POSITION
ADDRESS	0		1	2		3	4	5	6	7
1000		AStat			BStat		Ch	Con	Bias	Dis
1001			Peer_Speed			Int_enable	Fault		Reserved
1010						Reserved
1011						Reserved
1100						Reserved
1101						Reserved
1110						Reserved
1111						Reserved

Table 10−4. Page 0 (Port Status) Register Field Descriptions

FIELD	SIZE	TYPE		DESCRIPTION
AStat	2	R	TPA line state. This field indicates the TPA line state of the selected port, encoded as follows:
			Code	Arb Value
			11	Z
			10	0
			01	1
			00	invalid
BStat	2	R	TPB line state. This field indicates the TPB line state of the selected port. This field has the same encoding as
			the AStat field.
Ch	1	R	Child/parent status. A 1 indicates that the selected port is a child port. A 0 indicates that the selected port is
			the parent port. A disconnected, disabled, or suspended port is reported as a child port. The Ch bit is invalid
			after a bus reset until tree-ID has completed.
Con	1	R	Debounced port connection status. This bit indicates that the selected port is connected. The connection
			must be stable for the debounce time of approximately 341 ms for the Con bit to be set to 1. The Con bit is
			cleared to 0 by system (hardware) reset and is unaffected by bus reset.
			NOTE: The Con bit indicates that the port is physically connected to a peer PHY device, but the port is not
			necessarily active.
Bias	1	R	Debounced incoming cable bias status. A 1 indicates that the selected port is detecting incoming cable bias.
			The incoming cable bias must be stable for the debounce time of 52 ∝s for the Bias bit to be set to 1.
Dis	1	RW	Port disabled control. If the Dis bit is set to 1, the selected port is disabled. The Dis bit is cleared to 0 by
			system (hardware) reset (all ports are enabled for normal operation following system (hardware) reset). The
			Dis bit is not affected by bus reset.
Peer_Speed	3	R	Port peer speed. This field indicates the highest speed capability of the peer PHY device connected to the
			selected port, encoded as follows:
			Code	Peer Speed
			000	S100
			001	S200
			010	S400
			011−111	invalid
			The Peer_Speed field is invalid after a bus reset until self-ID has completed.
			NOTE: Peer speed codes higher than 010b (S400) are defined in IEEE Std 1394a-2000. However, the
			PCI7x21/PCI7x11 controller is only capable of detecting peer speeds up to S400.

10−4