Texas Instruments PCI7621, PCI7411, PCI7611, PCI7421 manual Syserr RCU

12.4 Status Register

The status register provides device information to the host system. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. Bits in this register may be read normally. A bit in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. See Table 12−3 for a complete description of the register contents.

Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Name								Status
Type	RCU	RCU	RCU	RCU	RCU	R	R	RCU	R	R	R	R	RU	R	R	R
Default	0	0	0	0	0	0	1	0	0	0	0	1	0	0	0	0
	Register:		Status
	Offset:		06h
	Type:		Read/Clear/Update, Read-only
	Default:		0210h

			Table 12−3. Status Register Description
BIT	FIELD NAME	TYPE			DESCRIPTION
15	PAR_ERR	RCU	Detected parity error. Bit 15 is set to 1 when either an address parity or data parity error is detected.
14	SYS_ERR	RCU	Signaled system error. Bit 14 is set to 1 when				is enabled and the SD host controller has signaled
						SERR
			a system error to the host.
13	MABORT	RCU	Received master abort. Bit 13 is set to 1 when a cycle initiated by the SD host controller on the PCI
			bus has been terminated by a master abort.
12	TABORT_REC	RCU	Received target abort. Bit 12 is set to 1 when a cycle initiated by the SD host controller on the PCI bus
			was terminated by a target abort.
11	TABORT_SIG	RCU	Signaled target abort. Bit 11 is set to 1 by the SD host controller when it terminates a transaction on
			the PCI bus with a target abort.
10−9	PCI_SPEED	R	DEVSEL timing. Bits 10 and 9 encode the timing of					and are hardwired to 01b, indicating that
							DEVSEL
			the SD host controller asserts this signal at a medium speed on nonconfiguration cycle accesses.
8	DATAPAR	RCU	Data parity error detected. Bit 8 is set to 1 when the following conditions have been met:
			a.	PERR	was asserted by any PCI device including the SD host controller.
			b. The SD host controller was the bus master during the data parity error.
			c. Bit 6 (PERR_EN) in the command register at offset 04h in the PCI configuration space
				(see Section 12.3) is set to 1.
7	FBB_CAP	R	Fast back-to-back capable. The SD host controller cannot accept fast back-to-back transactions;
			therefore, bit 7 is hardwired to 0.
6	UDF	R	User-definable features (UDF) supported. The SD host controller does not support the UDF; therefore,
			bit 6 is hardwired to 0.
5	66MHZ	R	66-MHz capable. The SD host controller operates at a maximum PCLK frequency of 33 MHz;
			therefore, bit 5 is hardwired to 0.
4	CAPLIST	R	Capabilities list. Bit 4 returns 1 when read, indicating that the SD host controller supports additional
			PCI capabilities.
3	INT_STATUS	RU	Interrupt status. This bit reflects the interrupt status of the function. Only when bit 10 (INT_DISABLE)
			in the command register (see Section 12.3) is a 0 and this bit is 1, is the function’s INTx signal asserted.
			Setting the INT_DISABLE bit to 1 has no effect on the state of this bit. This bit is set only when a valid
			interrupt condition exists. This bit is not set when an interrupt condition exists and signaling of that event
			is not enabled.
2−0	RSVD	R	Reserved. Bits 3−0 return 0s when read.

12−4