Texas Instruments PCI7411, PCI7421, PCI7611, PCI7621 8.30 Fairness Control Register

8−27
8.30 Fairness Control Register
The fairness control register provides a mechanism by which software can direct the host controller to transmit
multiple asynchronous requests during a fairness interval. See Table 8−22 for a complete description of the register
contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Fairness control
Type RRRRRRRRRRRRRRRR
Default 0000000000000000
Bit 15 14 13 12 11 109876543210
Name Fairness control
Type R R R R R R R R RW RW RW RW RW RW RW RW
Default 0000000000000000
Register: Fairness control
Offset: DCh
Type: Read-only
Default: 0000 0000h
Table 8−22. Fairness Control Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−8 RSVD R Reserved. Bits 31−8 return 0s when read.
7−0 pri_req RW This field specifies the maximum number of priority arbitration requests for asynchronous request
packets that the link is permitted to make of the PHY layer during a fairness interval. The default
value for this field is 00h.