Isochronous receive interrupt event | Texas Instruments PCI7411

8.25 Isochronous Receive Interrupt Event Register

The isochronous receive interrupt event set/clear register reflects the interrupt state of the isochronous receive contexts. An interrupt is generated on behalf of an isochronous receive context if an INPUT_* command completes and its interrupt bits are set to 1. Upon determining that the isochRx (bit 7) interrupt in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) has occurred, software can check this register to determine which context(s) caused the interrupt. The interrupt bits are set to 1 by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the set register. The only mechanism to clear a bit in this register is to write a 1 to the corresponding bit in the clear register. See Table 8−18 for a complete description of the register contents.

Bit	31	30	29	28	27	26		25	24	23	22		21	20	19	18	17	16

Name							Isochronous receive interrupt event

Type	R	R	R	R	R	R		R	R	R	R		R	R	R	R	R	R

Default	0	0	0	0	0	0		0	0	0	0		0	0	0	0	0	0

Bit	15		14	13	12		11		10		9	8		7	6		5	4	3	2	1	0

Name										Isochronous receive interrupt event

Type	R		R	R	R		R		R		R	R		R	R		R	R	RSC	RSC	RSC	RSC

Default	0		0	0	0		0		0		0	0		0	0		0	0	X	X	X	X

	Register:			Isochronous receive interrupt event
	Offset:			A0h	set register
				A4h	clear register [returns the contents of isochronous receive interrupt event register
					bit-wise ANDed with the isochronous receive mask register when read]
	Type:			Read/Set/Clear, Read-only
	Default:			0000 000Xh

Table 8−18. Isochronous Receive Interrupt Event Register Description

BIT	FIELD NAME	TYPE	DESCRIPTION

31−4	RSVD	R	Reserved. Bits 31−4 return 0s when read.

3	isoRecv3	RSC	Isochronous receive channel 3 caused the interrupt event register bit 7 (isochRx) interrupt.

2	isoRecv2	RSC	Isochronous receive channel 2 caused the interrupt event register bit 7 (isochRx) interrupt.

1	isoRecv1	RSC	Isochronous receive channel 1 caused the interrupt event register bit 7 (isochRx) interrupt.

0	isoRecv0	RSC	Isochronous receive channel 0 caused the interrupt event register bit 7 (isochRx) interrupt.

8−24

Image 204

Texas Instruments PCI7411, PCI7611 manual Isochronous Receive Interrupt Event Register, Isochronous receive interrupt event

Contents

Data Manual Important Notice Contents −10 PC Card Controller Programming Model −1 ExCA Compatibility Registers Functions 0 and 1 −1 Ohci Controller Programming Model −1 Ohci Registers −1Vii PHY Register Configuration 10−1 TI Extension Registers −1Viii Flash Media Controller Programming Model −1 SD Host Controller Programming Model −1 Smart Card Controller Programming Model −1 Electrical Characteristics −1 Mechanical Information 15−1 List of Illustrations Xii List of Tables Xiii Functions 0 and 1 PCI Configuration Register Map Xiv Title −13 Xvi Xvii Xviii Controller Functional Description 1 PCI7621 Controller 2 PCI7421 Controller 3 PCI7611 Controller PCI Bus Power Management Power Switch Interface4 PCI7411 Controller Multifunctional Terminals Features PCI Bus Interface Specification for PCI-to-CardBus Bridges PCI Local Bus Specification Revision Related Documents Trademarks Terms and Definitions Ordering Information−1. Terms and Definitions Term DefinitionsPage Terminal Descriptions −2. PCI7421 GHK/ZHK-Package Terminal Diagram −3. PCI7611 GHK/ZHK-Package Terminal Diagram −4. PCI7411 GHK/ZHK-Package Terminal Diagram −1. Signal Names by GHK Terminal Number Terminal Signal Name Number Breset ACC/BE2VCC VCC Acperr Scclk BCC/BE0 BCE1SCVCC5V Latch Grst Frame GNT PerrRIOUT/PME Vsspll −2. CardBus PC Card Signal Names Sorted Alphabetically Signal Name Terminal Number Sdcmd PC2TEST3Perr Trdy GND Prst GND −3 -Bit PC Card Signal Names Sorted Alphabetically Signal Terminal Signal Name Number −12 Detailed Terminal Descriptions −13 −4. Power Supply Terminals −14 −5. PC Card Power Switch Terminals −6. PCI System Terminals−15 −7. PCI Address and Data Terminals −16 −8. PCI Interface Control Terminals −17 −9. Multifunction and Miscellaneous Terminals −18 −10 -Bit PC Card Address and Data Terminals −11 -Bit PC Card Interface Control Terminals Stschg AOE −12. CardBus PC Card Interface System Terminals PCIO3 Vccb −13. CardBus PC Card Address and Data Terminals BCAD0 −14. CardBus PC Card Interface Control Terminals BCCD2 Cstop −15. Ieee 1394 Physical Layer Terminals −26 −16. SD/MMC Terminals −17. Memory Stick/PRO Terminals−27 −18. Smart Media/XD Terminals −28 −19. Smart Card Terminals † −30 Power Supply Sequencing EepromSD/MMC MS/MSPRO SD/MMC I/O Characteristics Clamping VoltagesPeripheral Component Interconnect PCI Interface 1 1394 PCI Bus Master Device Resets Serial Eeprom I2C BusVCC Grst Prst Pclk Functions 0 and 1 CardBus Subsystem Identification ROM A1 SCL A2 SDA VCC PC Card Applications Function 2 Ohci 1394 Subsystem IdentificationFunction 3 Flash Media Subsystem Identification Function 4 SD Host Subsystem Identification PC Card Insertion/Removal and Recognition Low Voltage CardBus Card DetectionUltraMedia Card Detection Flash Media Card Detection −2. PC Card-Card Detect and Voltage Sense ConnectionsCD2//CCD2 CD1//CCD1 VS2//CVS2 VS1//CVS1 VCC VPP/VCORE Internal Ring Oscillator −3. TPS2228 Control Logic-xVPP/VCORE−4. TPS2228 Control Logic-xVCC −5. TPS2226 Control Logic-xVPP LED Socket Activity Indicators Integrated Pullup Resistors for PC Card InterfaceSpkrout and Caudpwm Usage Spkrout Binaryspkr CardBus Socket Registers 11 48-MHz Clock Requirements−7. CardBus Socket Registers LED Accessing Serial-Bus Devices Through Software Serial Eeprom InterfaceSerial-Bus Interface Implementation Serial-Bus Interface Protocol −7. Serial-Bus Start/Stop Conditions and Bit Transfers −8. Serial-Bus Protocol Acknowledge Serial-Bus Eeprom Application −10. Serial-Bus Protocol-Byte Read −9. Eeprom Loading Map Serial ROM Byte Description OffsetGPE LinkEnh HCControl.Program Phy Enable PCI 2Ch, subsystem vendor ID, bytePCI 2Dh, subsystem vendor ID, byte PCI 2Eh, subsystem ID, byte Programmable Interrupt Subsystem PC Card Functional and Card Status Change Interrupts −10. Interrupt Mask and Flag RegistersCard Type Event Mask Flag Card Type Event Signal Description Interrupt Masks and Flags−11. PC Card Interrupt Events and Description Using Parallel IRQ Interrupts Using Parallel PCI Interrupts Power Management Overview Using Serialized Irqser InterruptsSMI Support in the PCI7x21/PCI7x11 Controller −12. Interrupt Pin Register Cross Reference 1 1394 Power Management Function CardBus PC Card Power Management Integrated Low-Dropout Voltage Regulator LDO-VRCardBus Functions 0 and 1 Clock Run Protocol Supply VCC Vren Vrport 5 16-Bit PC Card Power Management Suspend ModeRequirements for Suspend Mode Reset GNT Suspend Pclk Ring Indicate Cstsmask CSC Ringen RI CdresumeRienb Riout PCI Power Management −15. Power-Management RegistersPower-management control/status CSR CardBus Bridge Power Management −16. Function 2 Power-Management Registers−17. Function 3 Power-Management Registers −18. Function 4 Power-Management Registers Master List of PME Context Bits and Global Reset-Only Bits Acpi Support −28 −29 Ieee 1394 Application Information PHY Port Cable Connection Crystal Selection −31 Bus Reset Cphy + CBD−32 −33 −34 PCI Configuration Register Map Functions 0 −1. Bit Field Access Tag Descriptions−2. Functions 0 and 1 PCI Configuration Register Map Access TAG Name Meaning Vendor ID Register Vendor ID Device ID-Smart Card enabled Device ID Register Functions 0Device ID Command Register Command−3. Command Register Description BIT Signal Type Function Status Register Status−4. Status Register Description Revision ID Register Class Code RegisterCache Line Size Register Latency Timer Register Register Latency timerHeader Type Register Bist Register CardBus Socket Registers/ExCA Base Address Register Capability Pointer RegisterCardBus socket registers/ExCA base address Register Capability pointer Secondary Status Register Secondary status−5. Secondary Status Register Description PCI Bus Number Register CardBus Bus Number RegisterSubordinate Bus Number Register CardBus Latency Timer Register Register CardBus latency timerCardBus Memory Base Registers 0 Memory base registers 0 CardBus Memory Limit Registers 0 CardBus I/O Base Registers 0Memory limit registers 0 Base registers 0 CardBus I/O Limit Registers 0 Interrupt Line RegisterLimit registers 0 Register Interrupt line Interrupt Pin Register Interrupt pin − PCI function Bridge Control Register Interrupt pin−6. Interrupt Pin Register Cross Reference Bridge control Subsystem Vendor ID Register Subsystem vendor ID Subsystem ID Register PC Card 16-Bit I/F Legacy-Mode Base-Address RegisterSubsystem ID PC Card 16-bit I/F legacy-mode base-address System Control Register System control−8. System Control Register Description −8 . System Control Register Description Mccd Debounce Register Register Mccd debounce General Control Register General controlGeneral control −9. General Control Register Description General-Purpose Event Status Register General-purpose event status−10. General-Purpose Event Status Register Description General-Purpose Event Enable Register General-Purpose Input Register General-Purpose Output Register General-purpose output−13. General-Purpose Output Register Description Multifunction Routing Status Register Multifunction routing status−14. Multifunction Routing Status Register Description Retry Status Register Retry status−15. Retry Status Register Description Card Control Register Card control−16. Card Control Register Description Device Control Register Device control−17. Device Control Register Description Diagnostic Register Diagnostic−18. Diagnostic Register Description Capability ID Register Next Item Pointer RegisterRegister Capability ID Register Next item pointer Power Management Capabilities Register Power management capabilities−19. Power Management Capabilities Register Description Power Management Control/Status Register Power management control/status−20. Power Management Control/Status Register Description Power-Management Data Register Power management control/status bridge support extensionsPower-management data Bpccen Serial Bus Data Register Serial Bus Index RegisterSerial bus data −22. Serial Bus Data Register Description Serial Bus Slave Address Register Register Serial bus slave address−24. Serial Bus Slave Address Register Description Rwcmd Serial Bus Control/Status Register Serial bus control/status−25. Serial Bus Control/Status Register Description −38 ExCA Compatibility Registers Functions 0 −1. ExCA Register Access Through I/O −1. ExCA Registers and Offsets Exca Register Name PCI Memory Address Exca Offset Offset HEX ExCA Identification and Revision Register ExCA identification and revision−2. ExCA Identification and Revision Register Description Iftype ExCA Interface Status Register ExCA interface status−3. ExCA Interface Status Register Description ExCA Power Control Register ExCA power control−4. ExCA Power Control Register Description-82365SL Support ExCA Interrupt and General Control Register Register ExCA interrupt and general control−6. ExCA Interrupt and General Control Register Description ExCA Card Status-Change Register ExCA card status-change−7. ExCA Card Status-Change Register Description ExCA Card Status-Change Interrupt Configuration Register Register ExCA card status-change interrupt configuration ExCA Address Window Enable Register ExCA address window enable−9. ExCA Address Window Enable Register Description ExCA I/O Window Control Register ExCA I/O window control−10. ExCA I/O Window Control Register Description ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers ExCA I/O Windows 0 and 1 End-Address High-Byte Registers ExCA Memory Windows 0−4 Start-Address Low-Byte Registers ExCA Memory Windows 0−4 Start-Address High-Byte Registers ExCA Memory Windows 0−4 End-Address Low-Byte Registers ExCA Memory Windows 0−4 End-Address High-Byte Registers ExCA Memory Windows 0−4 Offset-Address Low-Byte Registers ExCA Memory Windows 0−4 Offset-Address High-Byte Registers ExCA Card Detect and General Control Register ExCA card detect and general control ExCA Global Control Register ExCA global control−15. ExCA Global Control Register Description ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers ExCA Memory Windows 0−4 Page Registers Register ExCA memory windows 0−4 CardBus Socket Registers Functions 0 Socket Event Register Socket event−2. Socket Event Register Description Socket Mask Register Socket mask−3. Socket Mask Register Description Socket Present State Register Socket present state−4. Socket Present State Register Description Socket Force Event Register Socket force event −5. Socket Force Event Register Description Socket Control Register Socket control−6. Socket Control Register Description Socket Power Management Register Socket power management−7. Socket Power Management Register Description −1. Function 2 Configuration Register Map Pmcsrbse Device ID Register −2. Command Register Description BIT Field Name Type Description −3. Status Register Description Latency Timer and Class Cache Line Size Register Latency timer and class cache line sizeClass Code and Revision ID Register Class code and revision ID Header Type and Bist Register Ohci Base Address Register TI Extension Base Address Register TI extension base address−8. TI Base Address Register Description CardBus CIS Base Address Register CardBus CIS Pointer RegisterCardBus CIS base address −9. CardBus CIS Base Address Register Description Power Management Capabilities Pointer Register Power management capabilities pointerSubsystem Identification Register Subsystem identification −11. Interrupt Line Register Description Register Interrupt pinBIT Field Name Type Description Intrline 01h Inta 02h Intb 03h Intc Bits Intsel Minimum Grant and Maximum Latency Register Ohci Control Register Capability ID and Next Item Pointer Registers Capability ID and next item pointerNextitem Capabilityid −16. Power Management Capabilities Register Description Power Management Control and Status Register Power Management Extension RegistersPower management control and status Power management extension PCI PHY Control Register PCI PHY control−19. PCI PHY Control Register Description Cnaout PCI Miscellaneous Configuration Register PCI miscellaneous configuration−20. PCI Miscellaneous Configuration Register Description Link Enhancement Control Register Link enhancement control−21. Link Enhancement Control Register Description Subsystem Access Register Subsystem access−22. Subsystem Access Register Description Subdevid Gpio Control Register Gpio control−23. Gpio Control Register Description Disablebmc GPIO0 GPIOENB1 GPIO1GPIODATA1 = GPIO0 −1. Ohci Register Map DMA Context Register Name Abbreviation OffsetGuid ROM Guidrom IsoRecvIntEventClear Isochronous receive interrupt mask IsoRecvIntMaskSetPhysicalRequestFilterHiClear Physical request filter low PhysicalRequestFilterLoSet Isochronous receive context command Asynchronous context control ContextControlSetContextControlClear Request Transmit Reserved Ohci Version Register Ohci version−2. Ohci Version Register Description Guid ROM Register −3. Guid ROM Register DescriptionGuid ROM RSU Asynchronous Transmit Retries Register CSR Data RegisterAsynchronous transmit retries −4. Asynchronous Transmit Retries Register Description CSR Compare Register CSR Control RegisterCSR compare CSR control Configuration ROM Header Register Configuration ROM header−6. Configuration ROM Header Register Description Bus Identification Register Bus Options Register Bus options−7. Bus Options Register Description Guid High Register Guid Low RegisterGuid high Guid low Configuration ROM Mapping Register Posted Write Address Low Register Posted Write Address High Register Posted write address high−10. Posted Write Address High Register Description Host Controller Control Register Host controller control−11. Host Controller Control Register Description RSU RSC Rscu Self-ID Buffer Pointer Register Self-ID buffer pointerLPS RSC Self-ID Count Register Self-ID count−12. Self-ID Count Register Description Isochronous Receive Channel Mask High Register Isochronous receive channel mask high Isochronous Receive Channel Mask Low Register Isochronous receive channel mask low Interrupt Event Register Interrupt event−15. Interrupt Event Register Description RSC Rscu Arrs Rscu Arrq Rscu MasterIntEnable Interrupt Mask RegisterInterrupt mask −16. Interrupt Mask Register Description Arrs RSC Arrq RSCGeneration Isochronous Transmit Interrupt Event Register Isochronous transmit interrupt event Isochronous Transmit Interrupt Mask Register Isochronous transmit interrupt mask Reserved. Bits 31−4 return 0s when read Isochronous Receive Interrupt Event RegisterIsochronous receive interrupt event Isochronous Receive Interrupt Mask Register Initial Bandwidth Available RegisterIsochronous receive interrupt mask Initial bandwidth available Initial Channels Available High Register Initial Channels Available Low Register Fairness Control Register Fairness control−22. Fairness Control Register Description Value for this field is 00h Link Control Register Link control−23. Link Control Register Description Node Identification Register Node identification−24. Node Identification Register Description PHY Layer Control Register PHY layer control−25. PHY Control Register Description Isochronous Cycle Timer Register Isochronous cycle timer−26. Isochronous Cycle Timer Register Description Asynchronous Request Filter High Register Asynchronous request filter high−27. Asynchronous Request Filter High Register Description From that node are accepted Asynchronous Request Filter Low Register Asynchronous request filter low−28. Asynchronous Request Filter Low Register Description Physical Request Filter High Register Physical request filter high−29. Physical Request Filter High Register Description PhysReqAllBusses That node are handled through the physical request context Physical Request Filter Low Register Physical Upper Bound Register Optional RegisterPhysical request filter low −30. Physical Request Filter Low Register Description Asynchronous Context Control Register Asynchronous context control−31. Asynchronous Context Control Register Description Rscu RSU Asynchronous Context Command Pointer Register Asynchronous context command pointerDescriptorAddress Isochronous Transmit Context Control Register Isochronous transmit context controlRSC RSU Isochronous Transmit Context Command Pointer Register Isochronous transmit context command pointerIsochronous Receive Context Control Register Isochronous receive context control When software clears bit 15 run Not be changed while bit 10 active or bit 15 run is set toMultiChanMode Context match register see .46 is ignored Isochronous Receive Context Command Pointer Register Isochronous receive context command pointerIsochronous receive context command pointer −43 Isochronous Receive Context Match Register Isochronous receive context match−35. Isochronous Receive Context Match Register Description DV and MPEG2 Timestamp Enhancements −1. TI Extension Register MapLink Enhancement Control Set Link Enhancement Control Clear A8Ch Isochronous Receive Digital Video Enhancements Isochronous Receive Digital Video Enhancements RegisterIsochronous receive digital video enhancements Reserved. Bits 7 and 6 return 0s when read 420h/424h see .44 is cleared toCIPStrip1 Ohci offset 420h/424h see .44 is cleared to Reserved. Bit 11 returns 0 when read 10 ‡ Link Enhancement RegisterLink enhancement −3. Link Enhancement Register Description Timestamp Offset Register Timestamp offset−4. Timestamp Offset Register Description Page −1. Base Register Configuration Base RegistersAddress BIT Position RHB IBR −2. Base Register Field Descriptions Field Size Type DescriptionRHB Long bus reset being performed LLC to service the interruptTimeout Is unaffected by bus reset −3. Page 0 Port Status Register Configuration Port Status Register−4. Page 0 Port Status Register Field Descriptions BIT Position Address −5. Page 1 Vendor ID Register Configuration Hardware reset and is unaffected by bus resetVendor Identification Register −6. Page 1 Vendor ID Register Field Descriptions −7. Page 7 Vendor-Dependent Register Configuration Vendor-Dependent Register−8. Page 7 Vendor-Dependent Register Field Descriptions NPA Power-Class Programming −9. Power Class DescriptionsNode does not need power and does not repeat power PC0-PC2 Description 10−8 −1. Function 3 Configuration Register Map Flash Media Controller Programming Model 11−2 Stepenb Pcispeed Devsel Programming interface. This field returns 00h when read Storage controllerIs deasserted Flash Media Base Address Register Flash media base address−7. Flash Media Base Address Register Description Subsystem Vendor Identification Register Capabilities Pointer RegisterSubsystem vendor identification Capabilities pointer −8. PCI Interrupt Pin Register Intsel Bits Useinta Intpin11−8 Minimum Grant Register Maximum Latency Register This field returns 00h when read −12. Power Management Capabilities Register Description Power Management Bridge Support Extension Register Pmestat RCUPmeen PME Rsvd Power Management Data Register Power management data−14. General Control Register −15. Subsystem Access Register Description SubsystemVendorIDRegister at PCI offset 2Ch 11−14 −16. Diagnostic Register Description DiagnosticTbdctrl Plln 11−16 −1. Function 4 Configuration Register Map Slot informationMaximum current 12−2 Therefore, bit 9 returns 0 when read Bit 5 returns 0 when readTransactions therefore, bit 4 returns 0 when read Bit 3 returns 0 when read Syserr RCU Peripheral DMA capabilities12−5 Memory-read line, and memory-read multiple transactions Read12−6 SD Host Base Address Register SD host base address−7. SD host Base Address Register Description Type 12.12 Interrupt Line Register 12−8 Space see Section 12−9 Slot Information Register Register Maximum latency−11. Maximum Latency Register Description Numberslots 12−11 −13. Power Management Capabilities Register Description Driver is able to use itController to generate PME Revision 12−12 Power management bridge support extension Enable. Enables SignalingRegister 12−13 −15. General Control Register 01 = Intb 10 = Intc 11 = IntdDmaen Dmasupport bit of each SD host socket is −16. Subsystem Access Register Description −17. Diagnostic Register DescriptionReserved. Bits 31−17 return 0s when read Register at PCI offset 2Ch Slot 0 3.3-V Maximum Current Register Slot 1 3.3-V Maximum Current RegisterSlot 2 3.3-V Maximum Current Register Slot 3 3.3-V Maximum Current Register Slot 4 3.3-V Maximum Current RegisterSlot 5 3.3-V Maximum Current Register 12−18 −1. Function 5 Configuration Register Map 1Ch−28h60h−FCh 13−2 Intdis Seren Is enabled and the Smart Card controller has Tabtsig RCUIntstat 13−4 Offset 08h Type Read-only Default 0780 0000h Smart Card Base Address Register Smart Card base address registerCard is a multifunction device Smart Card base address register Smart Card Base Address Register 1−4 Smart Card base address register 1−413−7 13.13 Interrupt Line Register 13−8 −7. PCI Interrupt Pin Register −8. Minimum Grant Register DescriptionSpace see Section 13−9 −9. Maximum Latency Register Description 13−10 −11. Power Management Capabilities Register Description PMED3HOTPMED2 PMED1 PMED0 D2SUPPORT PME Grst Rsvd Dstate13−12 Gated to reduce power consumption −13. General Control RegisterPin = 01 = Intb pin = 10 = Intc pin = 11 = Intd pin = Subsystem ID Alias Register Class Code Alias RegisterSubsystem ID alias −14. Subsystem ID Alias Register Description Smart Card Configuration 1 Register Smart Card configurationSmart Card configuration 13−15 −15. Smart Card Configuration 1 Register Description Smart Card Configuration 2 Register −16. Smart Card Configuration 2 Register DescriptionPwrupdelay Reserved. Bits 7−0 return 0s when read 13−17 13−18 Absolute Maximum Ratings Over Operating Temperature Ranges† Recommended Operating Conditions see NoteOperation MIN NOM MAX Unit Avdd VCC VDPLL15 VDPLL33 Vccp Recommended Operating Conditions TJ# Parameter Terminals Operation Test Conditions MIN MAX Unit 14.4.1 Device 14.4.2 Driver14.4.3 Receiver Parameter Test Condition MIN MAX Unit Switching Characteristics for PHY Port Interface Operating, Timing, and Switching CharacteristicsParameter Alternate Test Conditions MIN MAX Unit Parameter Test Conditions MIN TYP MAX Unit Mechanical Information 15−2 Package Option Addendum