Self-ID Count Register, Self-ID count | Texas Instruments PCI7421

8.18 Self-ID Count Register

The self-ID count register keeps a count of the number of times the bus self-ID process has occurred, flags self-ID packet errors, and keeps a count of the self-ID data in the self-ID buffer. See Table 8−12 for a complete description of the register contents.

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

Name								Self-ID count

Type	RU	R	R	R	R	R	R	R	RU	RU	RU	RU	RU	RU	RU	RU

Default	X	0	0	0	0	0	0	0	X	X	X	X	X	X	X	X

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Self-ID count

Type

R

R

R

R

R

RU

RU

RU

RU

RU

RU

RU

RU

RU

R

R

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Register:

Self-ID count

Offset:

68h

Type:

Read/Update, Read-only

Default:

X0XX 0000h

Table 8−12. Self-ID Count Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31

selfIDError

RU

When bit 31 is set to 1, an error was detected during the most recent self-ID packet reception. The

contents of the self-ID buffer are undefined. This bit is cleared after a self-ID reception in which no

errors are detected. Note that an error can be a hardware error or a host bus write error.

30−24

RSVD

R

Reserved. Bits 30−24 return 0s when read.

23−16

selfIDGeneration

RU

The value in this field increments each time a bus reset is detected. This field rolls over to 0 after

reaching 255.

15−11

RSVD

R

Reserved. Bits 15−11 return 0s when read.

10−2

selfIDSize

RU

This field indicates the number of quadlets that have been written into the self-ID buffer for the current

bits 23−16 (selfIDGeneration field). This includes the header quadlet and the self-ID data. This field

is cleared to 0s when the self-ID reception begins.

1−0

RSVD

R

Reserved. Bits 1 and 0 return 0s when read.

8−15

Image 195

Texas Instruments PCI7421, PCI7411, PCI7611, PCI7621 manual Self-ID count, 12. Self-ID Count Register Description

Contents

Data Manual Important Notice Contents −10 PC Card Controller Programming Model −1 ExCA Compatibility Registers Functions 0 and 1 −1 Ohci Controller Programming Model −1 Ohci Registers −1Vii PHY Register Configuration 10−1 TI Extension Registers −1Viii SD Host Controller Programming Model −1 Flash Media Controller Programming Model −1 Smart Card Controller Programming Model −1 Mechanical Information 15−1 Electrical Characteristics −1 Xii List of Illustrations Xiii List of Tables Xiv Functions 0 and 1 PCI Configuration Register Map Title −13 Xvi Xvii Xviii 1 PCI7621 Controller Controller Functional Description 3 PCI7611 Controller 2 PCI7421 Controller Multifunctional Terminals PCI Bus Power ManagementPower Switch Interface 4 PCI7411 Controller PCI Bus Interface Specification for PCI-to-CardBus Bridges Features Related Documents PCI Local Bus Specification Revision Trademarks Term Definitions Terms and DefinitionsOrdering Information −1. Terms and DefinitionsPage Terminal Descriptions −2. PCI7421 GHK/ZHK-Package Terminal Diagram −3. PCI7611 GHK/ZHK-Package Terminal Diagram −4. PCI7411 GHK/ZHK-Package Terminal Diagram Terminal Signal Name Number −1. Signal Names by GHK Terminal Number VCC Acperr BresetACC/BE2 VCC Latch ScclkBCC/BE0 BCE1 SCVCC5V Vsspll Grst FrameGNT Perr RIOUT/PME Signal Name Terminal Number −2. CardBus PC Card Signal Names Sorted Alphabetically Prst GND SdcmdPC2TEST3 Perr Trdy GND Signal Terminal Signal Name Number −3 -Bit PC Card Signal Names Sorted Alphabetically −12 −13 Detailed Terminal Descriptions −14 −4. Power Supply Terminals −5. PC Card Power Switch Terminals −6. PCI System Terminals−15 −16 −7. PCI Address and Data Terminals −17 −8. PCI Interface Control Terminals −18 −9. Multifunction and Miscellaneous Terminals −10 -Bit PC Card Address and Data Terminals Stschg −11 -Bit PC Card Interface Control Terminals AOE PCIO3 Vccb −12. CardBus PC Card Interface System Terminals BCAD0 −13. CardBus PC Card Address and Data Terminals BCCD2 −14. CardBus PC Card Interface Control Terminals Cstop −26 −15. Ieee 1394 Physical Layer Terminals −16. SD/MMC Terminals −17. Memory Stick/PRO Terminals−27 −28 −18. Smart Media/XD Terminals −19. Smart Card Terminals † −30 SD/MMC Power Supply SequencingEeprom SD/MMC MS/MSPRO 1 1394 PCI Bus Master I/O CharacteristicsClamping Voltages Peripheral Component Interconnect PCI Interface Device Resets Serial Eeprom I2C BusVCC Grst Prst Pclk ROM A1 SCL A2 SDA VCC Functions 0 and 1 CardBus Subsystem Identification Function 4 SD Host Subsystem Identification PC Card ApplicationsFunction 2 Ohci 1394 Subsystem Identification Function 3 Flash Media Subsystem Identification PC Card Insertion/Removal and Recognition Low Voltage CardBus Card DetectionUltraMedia Card Detection VCC VPP/VCORE Flash Media Card Detection−2. PC Card-Card Detect and Voltage Sense Connections CD2//CCD2 CD1//CCD1 VS2//CVS2 VS1//CVS1 −5. TPS2226 Control Logic-xVPP Internal Ring Oscillator−3. TPS2228 Control Logic-xVPP/VCORE −4. TPS2228 Control Logic-xVCC Spkrout Binaryspkr LED Socket Activity IndicatorsIntegrated Pullup Resistors for PC Card Interface Spkrout and Caudpwm Usage LED CardBus Socket Registers11 48-MHz Clock Requirements −7. CardBus Socket Registers Serial-Bus Interface Protocol Accessing Serial-Bus Devices Through SoftwareSerial Eeprom Interface Serial-Bus Interface Implementation −8. Serial-Bus Protocol Acknowledge −7. Serial-Bus Start/Stop Conditions and Bit Transfers −10. Serial-Bus Protocol-Byte Read Serial-Bus Eeprom Application −9. Eeprom Loading Map Serial ROM Byte Description OffsetGPE PCI 2Eh, subsystem ID, byte LinkEnh HCControl.Program Phy EnablePCI 2Ch, subsystem vendor ID, byte PCI 2Dh, subsystem vendor ID, byte Programmable Interrupt Subsystem PC Card Functional and Card Status Change Interrupts −10. Interrupt Mask and Flag RegistersCard Type Event Mask Flag Card Type Event Signal Description Interrupt Masks and Flags−11. PC Card Interrupt Events and Description Using Parallel PCI Interrupts Using Parallel IRQ Interrupts −12. Interrupt Pin Register Cross Reference Power Management OverviewUsing Serialized Irqser Interrupts SMI Support in the PCI7x21/PCI7x11 Controller 1 1394 Power Management Function Supply VCC Vren Vrport CardBus PC Card Power ManagementIntegrated Low-Dropout Voltage Regulator LDO-VR CardBus Functions 0 and 1 Clock Run Protocol Reset GNT Suspend Pclk 5 16-Bit PC Card Power ManagementSuspend Mode Requirements for Suspend Mode Ring Indicate Cstsmask CSC Ringen RI CdresumeRienb Riout PCI Power Management −15. Power-Management RegistersPower-management control/status CSR −18. Function 4 Power-Management Registers CardBus Bridge Power Management−16. Function 2 Power-Management Registers −17. Function 3 Power-Management Registers Acpi Support Master List of PME Context Bits and Global Reset-Only Bits −28 −29 PHY Port Cable Connection Ieee 1394 Application Information −31 Crystal Selection Bus Reset Cphy + CBD−32 −33 −34 Access TAG Name Meaning PCI Configuration Register Map Functions 0−1. Bit Field Access Tag Descriptions −2. Functions 0 and 1 PCI Configuration Register Map Vendor ID Vendor ID Register Device ID-Smart Card enabled Device ID Register Functions 0Device ID BIT Signal Type Function Command RegisterCommand −3. Command Register Description Status Register Status−4. Status Register Description Revision ID Register Class Code RegisterCache Line Size Register Bist Register Latency Timer RegisterRegister Latency timer Header Type Register Register Capability pointer CardBus Socket Registers/ExCA Base Address RegisterCapability Pointer Register CardBus socket registers/ExCA base address Secondary Status Register Secondary status−5. Secondary Status Register Description PCI Bus Number Register CardBus Bus Number RegisterSubordinate Bus Number Register Memory base registers 0 CardBus Latency Timer RegisterRegister CardBus latency timer CardBus Memory Base Registers 0 Base registers 0 CardBus Memory Limit Registers 0CardBus I/O Base Registers 0 Memory limit registers 0 Register Interrupt line CardBus I/O Limit Registers 0Interrupt Line Register Limit registers 0 Interrupt pin − PCI function Interrupt Pin Register Bridge control Bridge Control RegisterInterrupt pin −6. Interrupt Pin Register Cross Reference Subsystem vendor ID Subsystem Vendor ID Register PC Card 16-bit I/F legacy-mode base-address Subsystem ID RegisterPC Card 16-Bit I/F Legacy-Mode Base-Address Register Subsystem ID System Control Register System control−8. System Control Register Description −8 . System Control Register Description Register Mccd debounce Mccd Debounce Register General Control Register General controlGeneral control −9. General Control Register Description General-Purpose Event Status Register General-purpose event status−10. General-Purpose Event Status Register Description General-Purpose Input Register General-Purpose Event Enable Register General-Purpose Output Register General-purpose output−13. General-Purpose Output Register Description Multifunction Routing Status Register Multifunction routing status−14. Multifunction Routing Status Register Description Retry Status Register Retry status−15. Retry Status Register Description Card Control Register Card control−16. Card Control Register Description Device Control Register Device control−17. Device Control Register Description Diagnostic Register Diagnostic−18. Diagnostic Register Description Register Next item pointer Capability ID RegisterNext Item Pointer Register Register Capability ID Power Management Capabilities Register Power management capabilities−19. Power Management Capabilities Register Description Power Management Control/Status Register Power management control/status−20. Power Management Control/Status Register Description Bpccen Power-Management Data RegisterPower management control/status bridge support extensions Power-management data −22. Serial Bus Data Register Description Serial Bus Data RegisterSerial Bus Index Register Serial bus data Rwcmd Serial Bus Slave Address RegisterRegister Serial bus slave address −24. Serial Bus Slave Address Register Description Serial Bus Control/Status Register Serial bus control/status−25. Serial Bus Control/Status Register Description −38 ExCA Compatibility Registers Functions 0 −1. ExCA Register Access Through I/O −1. ExCA Registers and Offsets Exca Register Name PCI Memory Address Exca Offset Offset HEX Iftype ExCA Identification and Revision RegisterExCA identification and revision −2. ExCA Identification and Revision Register Description ExCA Interface Status Register ExCA interface status−3. ExCA Interface Status Register Description ExCA Power Control Register ExCA power control−4. ExCA Power Control Register Description-82365SL Support ExCA Interrupt and General Control Register Register ExCA interrupt and general control−6. ExCA Interrupt and General Control Register Description ExCA Card Status-Change Register ExCA card status-change−7. ExCA Card Status-Change Register Description Register ExCA card status-change interrupt configuration ExCA Card Status-Change Interrupt Configuration Register ExCA Address Window Enable Register ExCA address window enable−9. ExCA Address Window Enable Register Description ExCA I/O Window Control Register ExCA I/O window control−10. ExCA I/O Window Control Register Description ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers ExCA I/O Windows 0 and 1 End-Address High-Byte Registers ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers ExCA Memory Windows 0−4 Start-Address Low-Byte Registers ExCA Memory Windows 0−4 Start-Address High-Byte Registers ExCA Memory Windows 0−4 End-Address Low-Byte Registers ExCA Memory Windows 0−4 End-Address High-Byte Registers ExCA Memory Windows 0−4 Offset-Address Low-Byte Registers ExCA Memory Windows 0−4 Offset-Address High-Byte Registers ExCA card detect and general control ExCA Card Detect and General Control Register ExCA Global Control Register ExCA global control−15. ExCA Global Control Register Description ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers Register ExCA memory windows 0−4 ExCA Memory Windows 0−4 Page Registers CardBus Socket Registers Functions 0 Socket Event Register Socket event−2. Socket Event Register Description Socket Mask Register Socket mask−3. Socket Mask Register Description Socket Present State Register Socket present state−4. Socket Present State Register Description Socket force event Socket Force Event Register −5. Socket Force Event Register Description Socket Control Register Socket control−6. Socket Control Register Description Socket Power Management Register Socket power management−7. Socket Power Management Register Description Pmcsrbse −1. Function 2 Configuration Register Map Device ID Register BIT Field Name Type Description −2. Command Register Description −3. Status Register Description Class code and revision ID Latency Timer and Class Cache Line Size RegisterLatency timer and class cache line size Class Code and Revision ID Register Ohci Base Address Register Header Type and Bist Register TI Extension Base Address Register TI extension base address−8. TI Base Address Register Description −9. CardBus CIS Base Address Register Description CardBus CIS Base Address RegisterCardBus CIS Pointer Register CardBus CIS base address Subsystem identification Power Management Capabilities Pointer RegisterPower management capabilities pointer Subsystem Identification Register 01h Inta 02h Intb 03h Intc Bits Intsel −11. Interrupt Line Register DescriptionRegister Interrupt pin BIT Field Name Type Description Intrline Ohci Control Register Minimum Grant and Maximum Latency Register Capabilityid Capability ID and Next Item Pointer RegistersCapability ID and next item pointer Nextitem −16. Power Management Capabilities Register Description Power management extension Power Management Control and Status RegisterPower Management Extension Registers Power management control and status Cnaout PCI PHY Control RegisterPCI PHY control −19. PCI PHY Control Register Description PCI Miscellaneous Configuration Register PCI miscellaneous configuration−20. PCI Miscellaneous Configuration Register Description Link Enhancement Control Register Link enhancement control−21. Link Enhancement Control Register Description Subdevid Subsystem Access RegisterSubsystem access −22. Subsystem Access Register Description Gpio Control Register Gpio control−23. Gpio Control Register Description = GPIO0 Disablebmc GPIO0GPIOENB1 GPIO1 GPIODATA1 −1. Ohci Register Map DMA Context Register Name Abbreviation OffsetGuid ROM Guidrom Physical request filter low PhysicalRequestFilterLoSet IsoRecvIntEventClearIsochronous receive interrupt mask IsoRecvIntMaskSet PhysicalRequestFilterHiClear Request Transmit Reserved Isochronous receive context commandAsynchronous context control ContextControlSet ContextControlClear Ohci Version Register Ohci version−2. Ohci Version Register Description RSU Guid ROM Register−3. Guid ROM Register Description Guid ROM −4. Asynchronous Transmit Retries Register Description Asynchronous Transmit Retries RegisterCSR Data Register Asynchronous transmit retries CSR control CSR Compare RegisterCSR Control Register CSR compare Bus Identification Register Configuration ROM Header RegisterConfiguration ROM header −6. Configuration ROM Header Register Description Bus Options Register Bus options−7. Bus Options Register Description Guid low Guid High RegisterGuid Low Register Guid high Posted Write Address Low Register Configuration ROM Mapping Register Posted Write Address High Register Posted write address high−10. Posted Write Address High Register Description RSU RSC Rscu Host Controller Control RegisterHost controller control −11. Host Controller Control Register Description Self-ID Buffer Pointer Register Self-ID buffer pointerLPS RSC Self-ID Count Register Self-ID count−12. Self-ID Count Register Description Isochronous receive channel mask high Isochronous Receive Channel Mask High Register Isochronous receive channel mask low Isochronous Receive Channel Mask Low Register RSC Rscu Interrupt Event RegisterInterrupt event −15. Interrupt Event Register Description Arrq Rscu Arrs Rscu −16. Interrupt Mask Register Description MasterIntEnableInterrupt Mask Register Interrupt mask Arrs RSC Arrq RSCGeneration Isochronous transmit interrupt event Isochronous Transmit Interrupt Event Register Isochronous transmit interrupt mask Isochronous Transmit Interrupt Mask Register Reserved. Bits 31−4 return 0s when read Isochronous Receive Interrupt Event RegisterIsochronous receive interrupt event Initial bandwidth available Isochronous Receive Interrupt Mask RegisterInitial Bandwidth Available Register Isochronous receive interrupt mask Initial Channels Available Low Register Initial Channels Available High Register Value for this field is 00h Fairness Control RegisterFairness control −22. Fairness Control Register Description Link Control Register Link control−23. Link Control Register Description Node Identification Register Node identification−24. Node Identification Register Description PHY Layer Control Register PHY layer control−25. PHY Control Register Description Isochronous Cycle Timer Register Isochronous cycle timer−26. Isochronous Cycle Timer Register Description Asynchronous Request Filter High Register Asynchronous request filter high−27. Asynchronous Request Filter High Register Description From that node are accepted Asynchronous Request Filter Low Register Asynchronous request filter low−28. Asynchronous Request Filter Low Register Description PhysReqAllBusses Physical Request Filter High RegisterPhysical request filter high −29. Physical Request Filter High Register Description That node are handled through the physical request context −30. Physical Request Filter Low Register Description Physical Request Filter Low RegisterPhysical Upper Bound Register Optional Register Physical request filter low Rscu RSU Asynchronous Context Control RegisterAsynchronous context control −31. Asynchronous Context Control Register Description Asynchronous Context Command Pointer Register Asynchronous context command pointerDescriptorAddress Isochronous Transmit Context Control Register Isochronous transmit context controlRSC RSU Isochronous receive context control Isochronous Transmit Context Command Pointer RegisterIsochronous transmit context command pointer Isochronous Receive Context Control Register Context match register see .46 is ignored When software clears bit 15 runNot be changed while bit 10 active or bit 15 run is set to MultiChanMode −43 Isochronous Receive Context Command Pointer RegisterIsochronous receive context command pointer Isochronous receive context command pointer Isochronous Receive Context Match Register Isochronous receive context match−35. Isochronous Receive Context Match Register Description Link Enhancement Control Clear A8Ch DV and MPEG2 Timestamp Enhancements−1. TI Extension Register Map Link Enhancement Control Set Isochronous Receive Digital Video Enhancements Isochronous Receive Digital Video Enhancements RegisterIsochronous receive digital video enhancements Ohci offset 420h/424h see .44 is cleared to Reserved. Bits 7 and 6 return 0s when read420h/424h see .44 is cleared to CIPStrip1 −3. Link Enhancement Register Description Reserved. Bit 11 returns 0 when read 10 ‡Link Enhancement Register Link enhancement Timestamp Offset Register Timestamp offset−4. Timestamp Offset Register Description Page RHB IBR −1. Base Register ConfigurationBase Registers Address BIT Position −2. Base Register Field Descriptions Field Size Type DescriptionRHB Is unaffected by bus reset Long bus reset being performedLLC to service the interrupt Timeout BIT Position Address −3. Page 0 Port Status Register ConfigurationPort Status Register −4. Page 0 Port Status Register Field Descriptions −6. Page 1 Vendor ID Register Field Descriptions −5. Page 1 Vendor ID Register ConfigurationHardware reset and is unaffected by bus reset Vendor Identification Register NPA −7. Page 7 Vendor-Dependent Register ConfigurationVendor-Dependent Register −8. Page 7 Vendor-Dependent Register Field Descriptions PC0-PC2 Description Power-Class Programming−9. Power Class Descriptions Node does not need power and does not repeat power 10−8 Flash Media Controller Programming Model −1. Function 3 Configuration Register Map 11−2 Stepenb Pcispeed Devsel Programming interface. This field returns 00h when read Storage controllerIs deasserted Flash Media Base Address Register Flash media base address−7. Flash Media Base Address Register Description Capabilities pointer Subsystem Vendor Identification RegisterCapabilities Pointer Register Subsystem vendor identification −8. PCI Interrupt Pin Register Intsel Bits Useinta Intpin11−8 Maximum Latency Register Minimum Grant Register This field returns 00h when read −12. Power Management Capabilities Register Description PME Rsvd Power Management Bridge Support Extension RegisterPmestat RCU Pmeen Power Management Data Register Power management data−14. General Control Register −15. Subsystem Access Register Description SubsystemVendorIDRegister at PCI offset 2Ch 11−14 Plln −16. Diagnostic Register DescriptionDiagnostic Tbdctrl 11−16 −1. Function 4 Configuration Register Map Slot informationMaximum current 12−2 Bit 3 returns 0 when read Therefore, bit 9 returns 0 when readBit 5 returns 0 when read Transactions therefore, bit 4 returns 0 when read Syserr RCU Peripheral DMA capabilities12−5 Memory-read line, and memory-read multiple transactions Read12−6 Type SD Host Base Address RegisterSD host base address −7. SD host Base Address Register Description 12−8 12.12 Interrupt Line Register Space see Section 12−9 Numberslots Slot Information RegisterRegister Maximum latency −11. Maximum Latency Register Description 12−11 Revision 12−12 −13. Power Management Capabilities Register DescriptionDriver is able to use it Controller to generate PME 12−13 Power management bridge support extensionEnable. Enables Signaling Register Dmasupport bit of each SD host socket is −15. General Control Register01 = Intb 10 = Intc 11 = Intd Dmaen Register at PCI offset 2Ch −16. Subsystem Access Register Description−17. Diagnostic Register Description Reserved. Bits 31−17 return 0s when read Slot 0 3.3-V Maximum Current Register Slot 1 3.3-V Maximum Current RegisterSlot 2 3.3-V Maximum Current Register Slot 3 3.3-V Maximum Current Register Slot 4 3.3-V Maximum Current RegisterSlot 5 3.3-V Maximum Current Register 12−18 −1. Function 5 Configuration Register Map 1Ch−28h60h−FCh 13−2 Seren Intdis 13−4 Is enabled and the Smart Card controller hasTabtsig RCU Intstat Offset 08h Type Read-only Default 0780 0000h Smart Card base address register Smart Card Base Address RegisterSmart Card base address register Card is a multifunction device Smart Card Base Address Register 1−4 Smart Card base address register 1−413−7 13−8 13.13 Interrupt Line Register −7. PCI Interrupt Pin Register −8. Minimum Grant Register DescriptionSpace see Section 13−9 13−10 −9. Maximum Latency Register Description PMED1 PMED0 D2SUPPORT −11. Power Management Capabilities Register DescriptionPMED3HOT PMED2 PME Grst Rsvd Dstate13−12 Gated to reduce power consumption −13. General Control RegisterPin = 01 = Intb pin = 10 = Intc pin = 11 = Intd pin = −14. Subsystem ID Alias Register Description Subsystem ID Alias RegisterClass Code Alias Register Subsystem ID alias 13−15 Smart Card Configuration 1 RegisterSmart Card configuration Smart Card configuration −15. Smart Card Configuration 1 Register Description Reserved. Bits 7−0 return 0s when read 13−17 Smart Card Configuration 2 Register−16. Smart Card Configuration 2 Register Description Pwrupdelay 13−18 Avdd VCC VDPLL15 VDPLL33 Vccp Absolute Maximum Ratings Over Operating Temperature Ranges†Recommended Operating Conditions see Note Operation MIN NOM MAX Unit Recommended Operating Conditions TJ# Parameter Terminals Operation Test Conditions MIN MAX Unit Parameter Test Condition MIN MAX Unit 14.4.1 Device14.4.2 Driver 14.4.3 Receiver Parameter Test Conditions MIN TYP MAX Unit Switching Characteristics for PHY Port InterfaceOperating, Timing, and Switching Characteristics Parameter Alternate Test Conditions MIN MAX Unit Mechanical Information 15−2 Package Option Addendum