Texas Instruments PCI7611, PCI7411, PCI7621 13. CardBus PC Card Address and Data Terminals, BCAD0

Table 2−13. CardBus PC Card Address and Data Terminals

External components are not applicable for the 16-bit PC Card address and data terminals. If any CardBus PC Card address and data terminal is unused, then the terminal may be left floating.

SKT A TERMINAL		SKT B TERMINAL†		DESCRIPTION		I/O	INPUT	OUTPUT	POWER
NAME	NO.	NAME	NO.			TYPE			RAIL
A_CAD31	D01	B_CAD31	B15
A_CAD30	C01	B_CAD30	A16
A_CAD29	D03	B_CAD29	B16
A_CAD28	C02	B_CAD28	A17
A_CAD27	B01	B_CAD27	C16
A_CAD26	B04	B_CAD26	D17
A_CAD25	A04	B_CAD25	C19
A_CAD24	E06	B_CAD24	D18
A_CAD23	B05	B_CAD23	E17
A_CAD22	C06	B_CAD22	E19
A_CAD21	B06	B_CAD21	G15
A_CAD20	G09	B_CAD20	F18
A_CAD19	C07	B_CAD19	H14
A_CAD18	B07	B_CAD18	H15
A_CAD17	A07	B_CAD17	G17	CardBus address and data. These signals make up the multiplexed
A_CAD16	A10	B_CAD16	K17	CardBus address and data bus on the CardBus interface. During					VCCA/
				the address phase of a CardBus cycle, CAD31−CAD0 contain a		I/O	PCII7	PCIO7
A_CAD15	E11	B_CAD15	L13						VCCB
				32-bit address. During the data phase of a CardBus cycle,
A_CAD14	G11	B_CAD14	K18	CAD31−CAD0 contain data. CAD31 is the most significant bit.
A_CAD13	C11	B_CAD13	L15
A_CAD12	B11	B_CAD12	L17
A_CAD11	C12	B_CAD11	L18
A_CAD10	B12	B_CAD10	L19
A_CAD9	A12	B_CAD9	M17
A_CAD8	E12	B_CAD8	M14
A_CAD7	C13	B_CAD7	M15
A_CAD6	F12	B_CAD6	N19
A_CAD5	A13	B_CAD5	N18
A_CAD4	C14	B_CAD4	N15
A_CAD3	E13	B_CAD3	M13
A_CAD2	A14	B_CAD2	P18
A_CAD1	B14	B_CAD1	P17
A_CAD0	E14	B_CAD0	P19
				CardBus bus commands and byte enables.
					CC/BE3−CC/BE0 are
				multiplexed on the same CardBus terminals. During the address
	C05		F15
A_CC/BE3		B_CC/BE3		phase of a CardBus cycle, CC/BE3−CC/BE0 define the bus
	F09		G18	command. During the data phase, this 4-bit bus is used as byte
A_CC/BE2		B_CC/BE2				I/O			VCCA/
				enables. The byte enables determine which byte paths of the full			PCII7	PCIO7
	B10		K14						VCCB
A_CC/BE1		B_CC/BE1
				32-bit data bus carry meaningful data. CC/BE0 applies to byte 0
A_CC/BE0	G12	B_CC/BE0	M18	(CAD7−CAD0), CC/BE1 applies to byte 1 (CAD15−CAD8),
				CC/BE2 applies to byte 2 (CAD23−CAD16), and CC/BE3 applies to
				byte 3 (CAD31−CAD24).
				CardBus parity. In all CardBus read and write cycles, the controller
				calculates even parity across the CAD and CC/BE buses. As an
A_CPAR	G10	B_CPAR	K13	initiator during CardBus cycles, the controller outputs CPAR with a		I/O	PCII7	PCIO7	VCCA/
				one-CCLK delay. As a target during CardBus cycles, the controller					VCCB
				compares its calculated parity to the parity indicator of the initiator;
				a compare error results in a parity error assertion.

†These terminals are reserved for the PCI7611 and PCI7411 controllers.

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