Texas Instruments PCI7421, PCI7411, PCI7611, PCI7621 manual Power Management Control/Status Register

4.44 Power Management Control/Status Register

The power management control/status register determines and changes the current power state of the PCI7x21/PCI7x11 CardBus function. The contents of this register are not affected by the internally generated reset caused by the transition from the D3hot to D0 state. See Table 4−20 for a complete description of the register contents.

All PCI registers, ExCA registers, and CardBus registers are reset as a result of a D3hot-to-D0 state transition, with

the exception of the PME context bits (if PME is enabled) and the GRST only bits.

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Power management control/status

Type

RWC

R

R

R

R

R

R

RW

R

R

R

R

R

R

RW

RW

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Register:

Power management control/status

Offset:

A4h (Functions 0, 1)

Type:

Read-only, Read/Write, Read/Write/Clear

Default:

0000h

Table 4−20. Power Management Control/Status Register Description

BIT

SIGNAL

TYPE

FUNCTION

PME status. This bit is set when the CardBus function would normally assert the

PME

signal, independent

15 †

PMESTAT

RC

of the state of the PME_EN bit. This bit is cleared by a writeback of 1, and this also clears the PME signal

if

PME

was asserted by this function. Writing a 0 to this bit has no effect.

14−13

DATASCALE

R

This 2-bit field returns 0s when read. The CardBus function does not return any dynamic data.

12−9

DATASEL

R

Data select. This 4-bit field returns 0s when read. The CardBus function does not return any dynamic data.

8 ‡

PME_ENABLE

RW

This bit enables the function to assert

PME

. If this bit is cleared, then assertion of

PME

is disabled. This

bit is not cleared by the assertion of PRST. It is only cleared by the assertion of GRST.

7−2

RSVD

R

Reserved. These bits return 0s when read.

Power state. This 2-bit field is used both to determine the current power state of a function and to set the

function into a new power state. This field is encoded as:

1−0

PWRSTATE

RW

00 = D0

01 = D1

10 = D2

11 = D3hot

†One or more bits in this register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or GRST.

‡This bit is cleared only by the assertion of GRST.

4−33