Data Manual
 Important Notice
 Contents
 −10
 PC Card Controller Programming Model −1
 ExCA Compatibility Registers Functions 0 and 1 −1
 Ohci Registers −1
Ohci Controller Programming Model −1
Vii
 TI Extension Registers −1
PHY Register Configuration 10−1
Viii
 Flash Media Controller Programming Model −1
SD Host Controller Programming Model −1
 Smart Card Controller Programming Model −1
 Electrical Characteristics −1
Mechanical Information 15−1
 List of Illustrations
Xii
 List of Tables
Xiii
 Functions 0 and 1 PCI Configuration Register Map
Xiv
 Title −13
 Xvi
 Xvii
 Xviii
 Controller Functional Description
1 PCI7621 Controller
 2 PCI7421 Controller
3 PCI7611 Controller
 4 PCI7411 Controller
PCI Bus Power Management
Power Switch Interface
Multifunctional Terminals
 Features
PCI Bus Interface Specification for PCI-to-CardBus Bridges
 PCI Local Bus Specification Revision
Related Documents
 Trademarks
 −1. Terms and Definitions
Terms and Definitions
Ordering Information
Term Definitions
Page
 Terminal Descriptions
 −2. PCI7421 GHK/ZHK-Package Terminal Diagram
 −3. PCI7611 GHK/ZHK-Package Terminal Diagram
 −4. PCI7411 GHK/ZHK-Package Terminal Diagram
 −1. Signal Names by GHK Terminal Number
Terminal Signal Name Number
 VCC
Breset
ACC/BE2
VCC Acperr
 SCVCC5V
Scclk
BCC/BE0 BCE1
Latch
 RIOUT/PME
Grst Frame
GNT Perr
Vsspll
 −2. CardBus PC Card Signal Names Sorted Alphabetically
Signal Name Terminal Number
 Perr Trdy GND
Sdcmd
PC2TEST3
Prst GND
 −3 -Bit PC Card Signal Names Sorted Alphabetically
Signal Terminal Signal Name Number
 −12
 Detailed Terminal Descriptions
−13
 −4. Power Supply Terminals
−14
 −6. PCI System Terminals
−5. PC Card Power Switch Terminals
−15
 −7. PCI Address and Data Terminals
−16
 −8. PCI Interface Control Terminals
−17
 −9. Multifunction and Miscellaneous Terminals
−18
 −10 -Bit PC Card Address and Data Terminals
 −11 -Bit PC Card Interface Control Terminals
Stschg
 AOE
 −12. CardBus PC Card Interface System Terminals
PCIO3 Vccb
 −13. CardBus PC Card Address and Data Terminals
BCAD0
 −14. CardBus PC Card Interface Control Terminals
BCCD2
 Cstop
 −15. Ieee 1394 Physical Layer Terminals
−26
 −17. Memory Stick/PRO Terminals
−16. SD/MMC Terminals
−27
 −18. Smart Media/XD Terminals
−28
 −19. Smart Card Terminals †
 −30
 SD/MMC MS/MSPRO
Power Supply Sequencing
Eeprom
SD/MMC
 Peripheral Component Interconnect PCI Interface
I/O Characteristics
Clamping Voltages
1 1394 PCI Bus Master
 Serial Eeprom I2C Bus
Device Resets
VCC Grst Prst Pclk
 Functions 0 and 1 CardBus Subsystem Identification
ROM A1 SCL A2 SDA VCC
 Function 3 Flash Media Subsystem Identification
PC Card Applications
Function 2 Ohci 1394 Subsystem Identification
Function 4 SD Host Subsystem Identification
 Low Voltage CardBus Card Detection
PC Card Insertion/Removal and Recognition
UltraMedia Card Detection
 CD2//CCD2 CD1//CCD1 VS2//CVS2 VS1//CVS1
Flash Media Card Detection
−2. PC Card-Card Detect and Voltage Sense Connections
VCC VPP/VCORE
 −4. TPS2228 Control Logic-xVCC
Internal Ring Oscillator
−3. TPS2228 Control Logic-xVPP/VCORE
−5. TPS2226 Control Logic-xVPP
 Spkrout and Caudpwm Usage
LED Socket Activity Indicators
Integrated Pullup Resistors for PC Card Interface
Spkrout Binaryspkr
 −7. CardBus Socket Registers
CardBus Socket Registers
11 48-MHz Clock Requirements
LED
 Serial-Bus Interface Implementation
Accessing Serial-Bus Devices Through Software
Serial Eeprom Interface
Serial-Bus Interface Protocol
 −7. Serial-Bus Start/Stop Conditions and Bit Transfers
−8. Serial-Bus Protocol Acknowledge
 Serial-Bus Eeprom Application
−10. Serial-Bus Protocol-Byte Read
 Serial ROM Byte Description Offset
−9. Eeprom Loading Map
GPE
 PCI 2Dh, subsystem vendor ID, byte
LinkEnh HCControl.Program Phy Enable
PCI 2Ch, subsystem vendor ID, byte
PCI 2Eh, subsystem ID, byte
 Programmable Interrupt Subsystem
 −10. Interrupt Mask and Flag Registers
PC Card Functional and Card Status Change Interrupts
Card Type Event Mask Flag
 Interrupt Masks and Flags
Card Type Event Signal Description
−11. PC Card Interrupt Events and Description
 Using Parallel IRQ Interrupts
Using Parallel PCI Interrupts
 SMI Support in the PCI7x21/PCI7x11 Controller
Power Management Overview
Using Serialized Irqser Interrupts
−12. Interrupt Pin Register Cross Reference
 1 1394 Power Management Function
 CardBus Functions 0 and 1 Clock Run Protocol
CardBus PC Card Power Management
Integrated Low-Dropout Voltage Regulator LDO-VR
Supply VCC Vren Vrport
 Requirements for Suspend Mode
5 16-Bit PC Card Power Management
Suspend Mode
Reset GNT Suspend Pclk
 Cstsmask CSC Ringen RI Cdresume
Ring Indicate
Rienb Riout
 −15. Power-Management Registers
PCI Power Management
Power-management control/status CSR
 −17. Function 3 Power-Management Registers
CardBus Bridge Power Management
−16. Function 2 Power-Management Registers
−18. Function 4 Power-Management Registers
 Master List of PME Context Bits and Global Reset-Only Bits
Acpi Support
 −28
 −29
 Ieee 1394 Application Information
PHY Port Cable Connection
 Crystal Selection
−31
 Cphy + CBD
Bus Reset
−32
 −33
 −34
 −2. Functions 0 and 1 PCI Configuration Register Map
PCI Configuration Register Map Functions 0
−1. Bit Field Access Tag Descriptions
Access TAG Name Meaning
 Vendor ID Register
Vendor ID
 Device ID Register Functions 0
Device ID-Smart Card enabled
Device ID
 −3. Command Register Description
Command Register
Command
BIT Signal Type Function
 Status
Status Register
−4. Status Register Description
 Class Code Register
Revision ID Register
Cache Line Size Register
 Header Type Register
Latency Timer Register
Register Latency timer
Bist Register
 CardBus socket registers/ExCA base address
CardBus Socket Registers/ExCA Base Address Register
Capability Pointer Register
Register Capability pointer
 Secondary status
Secondary Status Register
−5. Secondary Status Register Description
 CardBus Bus Number Register
PCI Bus Number Register
Subordinate Bus Number Register
 CardBus Memory Base Registers 0
CardBus Latency Timer Register
Register CardBus latency timer
Memory base registers 0
 Memory limit registers 0
CardBus Memory Limit Registers 0
CardBus I/O Base Registers 0
Base registers 0
 Limit registers 0
CardBus I/O Limit Registers 0
Interrupt Line Register
Register Interrupt line
 Interrupt Pin Register
Interrupt pin − PCI function
 −6. Interrupt Pin Register Cross Reference
Bridge Control Register
Interrupt pin
Bridge control
 Subsystem Vendor ID Register
Subsystem vendor ID
 Subsystem ID
Subsystem ID Register
PC Card 16-Bit I/F Legacy-Mode Base-Address Register
PC Card 16-bit I/F legacy-mode base-address
 System control
System Control Register
−8. System Control Register Description
 −8 . System Control Register Description
 Mccd Debounce Register
Register Mccd debounce
 General control
General Control Register
General control
 −9. General Control Register Description
 General-purpose event status
General-Purpose Event Status Register
−10. General-Purpose Event Status Register Description
 General-Purpose Event Enable Register
General-Purpose Input Register
 General-purpose output
General-Purpose Output Register
−13. General-Purpose Output Register Description
 Multifunction routing status
Multifunction Routing Status Register
−14. Multifunction Routing Status Register Description
 Retry status
Retry Status Register
−15. Retry Status Register Description
 Card control
Card Control Register
−16. Card Control Register Description
 Device control
Device Control Register
−17. Device Control Register Description
 Diagnostic
Diagnostic Register
−18. Diagnostic Register Description
 Register Capability ID
Capability ID Register
Next Item Pointer Register
Register Next item pointer
 Power management capabilities
Power Management Capabilities Register
−19. Power Management Capabilities Register Description
 Power management control/status
Power Management Control/Status Register
−20. Power Management Control/Status Register Description
 Power-management data
Power-Management Data Register
Power management control/status bridge support extensions
Bpccen
 Serial bus data
Serial Bus Data Register
Serial Bus Index Register
−22. Serial Bus Data Register Description
 −24. Serial Bus Slave Address Register Description
Serial Bus Slave Address Register
Register Serial bus slave address
Rwcmd
 Serial bus control/status
Serial Bus Control/Status Register
−25. Serial Bus Control/Status Register Description
 −38
 ExCA Compatibility Registers Functions 0
 −1. ExCA Register Access Through I/O
 −1. ExCA Registers and Offsets
 Exca Register Name PCI Memory Address Exca Offset Offset HEX
 −2. ExCA Identification and Revision Register Description
ExCA Identification and Revision Register
ExCA identification and revision
Iftype
 ExCA interface status
ExCA Interface Status Register
−3. ExCA Interface Status Register Description
 ExCA power control
ExCA Power Control Register
−4. ExCA Power Control Register Description-82365SL Support
 Register ExCA interrupt and general control
ExCA Interrupt and General Control Register
−6. ExCA Interrupt and General Control Register Description
 ExCA card status-change
ExCA Card Status-Change Register
−7. ExCA Card Status-Change Register Description
 ExCA Card Status-Change Interrupt Configuration Register
Register ExCA card status-change interrupt configuration
 ExCA address window enable
ExCA Address Window Enable Register
−9. ExCA Address Window Enable Register Description
 ExCA I/O window control
ExCA I/O Window Control Register
−10. ExCA I/O Window Control Register Description
 ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers
ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers
 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers
ExCA I/O Windows 0 and 1 End-Address High-Byte Registers
 ExCA Memory Windows 0−4 Start-Address Low-Byte Registers
 ExCA Memory Windows 0−4 Start-Address High-Byte Registers
 ExCA Memory Windows 0−4 End-Address Low-Byte Registers
 ExCA Memory Windows 0−4 End-Address High-Byte Registers
 ExCA Memory Windows 0−4 Offset-Address Low-Byte Registers
 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers
 ExCA Card Detect and General Control Register
ExCA card detect and general control
 ExCA global control
ExCA Global Control Register
−15. ExCA Global Control Register Description
 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers
ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers
 ExCA Memory Windows 0−4 Page Registers
Register ExCA memory windows 0−4
 CardBus Socket Registers Functions 0
 Socket event
Socket Event Register
−2. Socket Event Register Description
 Socket mask
Socket Mask Register
−3. Socket Mask Register Description
 Socket present state
Socket Present State Register
−4. Socket Present State Register Description
 Socket Force Event Register
Socket force event
 −5. Socket Force Event Register Description
 Socket control
Socket Control Register
−6. Socket Control Register Description
 Socket power management
Socket Power Management Register
−7. Socket Power Management Register Description
 −1. Function 2 Configuration Register Map
Pmcsrbse
 Device ID Register
 −2. Command Register Description
BIT Field Name Type Description
 −3. Status Register Description
 Class Code and Revision ID Register
Latency Timer and Class Cache Line Size Register
Latency timer and class cache line size
Class code and revision ID
 Header Type and Bist Register
Ohci Base Address Register
 TI extension base address
TI Extension Base Address Register
−8. TI Base Address Register Description
 CardBus CIS base address
CardBus CIS Base Address Register
CardBus CIS Pointer Register
−9. CardBus CIS Base Address Register Description
 Subsystem Identification Register
Power Management Capabilities Pointer Register
Power management capabilities pointer
Subsystem identification
 BIT Field Name Type Description Intrline
−11. Interrupt Line Register Description
Register Interrupt pin
01h Inta 02h Intb 03h Intc Bits Intsel
 Minimum Grant and Maximum Latency Register
Ohci Control Register
 Nextitem
Capability ID and Next Item Pointer Registers
Capability ID and next item pointer
Capabilityid
 −16. Power Management Capabilities Register Description
 Power management control and status
Power Management Control and Status Register
Power Management Extension Registers
Power management extension
 −19. PCI PHY Control Register Description
PCI PHY Control Register
PCI PHY control
Cnaout
 PCI miscellaneous configuration
PCI Miscellaneous Configuration Register
−20. PCI Miscellaneous Configuration Register Description
 Link enhancement control
Link Enhancement Control Register
−21. Link Enhancement Control Register Description
 −22. Subsystem Access Register Description
Subsystem Access Register
Subsystem access
Subdevid
 Gpio control
Gpio Control Register
−23. Gpio Control Register Description
 GPIODATA1
Disablebmc GPIO0
GPIOENB1 GPIO1
= GPIO0
 DMA Context Register Name Abbreviation Offset
−1. Ohci Register Map
Guid ROM Guidrom
 PhysicalRequestFilterHiClear
IsoRecvIntEventClear
Isochronous receive interrupt mask IsoRecvIntMaskSet
Physical request filter low PhysicalRequestFilterLoSet
 ContextControlClear
Isochronous receive context command
Asynchronous context control ContextControlSet
Request Transmit Reserved
 Ohci version
Ohci Version Register
−2. Ohci Version Register Description
 Guid ROM
Guid ROM Register
−3. Guid ROM Register Description
RSU
 Asynchronous transmit retries
Asynchronous Transmit Retries Register
CSR Data Register
−4. Asynchronous Transmit Retries Register Description
 CSR compare
CSR Compare Register
CSR Control Register
CSR control
 −6. Configuration ROM Header Register Description
Configuration ROM Header Register
Configuration ROM header
Bus Identification Register
 Bus options
Bus Options Register
−7. Bus Options Register Description
 Guid high
Guid High Register
Guid Low Register
Guid low
 Configuration ROM Mapping Register
Posted Write Address Low Register
 Posted write address high
Posted Write Address High Register
−10. Posted Write Address High Register Description
 −11. Host Controller Control Register Description
Host Controller Control Register
Host controller control
RSU RSC Rscu
 Self-ID buffer pointer
Self-ID Buffer Pointer Register
LPS RSC
 Self-ID count
Self-ID Count Register
−12. Self-ID Count Register Description
 Isochronous Receive Channel Mask High Register
Isochronous receive channel mask high
 Isochronous Receive Channel Mask Low Register
Isochronous receive channel mask low
 −15. Interrupt Event Register Description
Interrupt Event Register
Interrupt event
RSC Rscu
 Arrs Rscu
Arrq Rscu
 Interrupt mask
MasterIntEnable
Interrupt Mask Register
−16. Interrupt Mask Register Description
 Arrq RSC
Arrs RSC
Generation
 Isochronous Transmit Interrupt Event Register
Isochronous transmit interrupt event
 Isochronous Transmit Interrupt Mask Register
Isochronous transmit interrupt mask
 Isochronous Receive Interrupt Event Register
Reserved. Bits 31−4 return 0s when read
Isochronous receive interrupt event
 Isochronous receive interrupt mask
Isochronous Receive Interrupt Mask Register
Initial Bandwidth Available Register
Initial bandwidth available
 Initial Channels Available High Register
Initial Channels Available Low Register
 −22. Fairness Control Register Description
Fairness Control Register
Fairness control
Value for this field is 00h
 Link control
Link Control Register
−23. Link Control Register Description
 Node identification
Node Identification Register
−24. Node Identification Register Description
 PHY layer control
PHY Layer Control Register
−25. PHY Control Register Description
 Isochronous cycle timer
Isochronous Cycle Timer Register
−26. Isochronous Cycle Timer Register Description
 Asynchronous request filter high
Asynchronous Request Filter High Register
−27. Asynchronous Request Filter High Register Description
 From that node are accepted
 Asynchronous request filter low
Asynchronous Request Filter Low Register
−28. Asynchronous Request Filter Low Register Description
 −29. Physical Request Filter High Register Description
Physical Request Filter High Register
Physical request filter high
PhysReqAllBusses
 That node are handled through the physical request context
 Physical request filter low
Physical Request Filter Low Register
Physical Upper Bound Register Optional Register
−30. Physical Request Filter Low Register Description
 −31. Asynchronous Context Control Register Description
Asynchronous Context Control Register
Asynchronous context control
Rscu RSU
 Asynchronous context command pointer
Asynchronous Context Command Pointer Register
DescriptorAddress
 Isochronous transmit context control
Isochronous Transmit Context Control Register
RSC RSU
 Isochronous Receive Context Control Register
Isochronous Transmit Context Command Pointer Register
Isochronous transmit context command pointer
Isochronous receive context control
 MultiChanMode
When software clears bit 15 run
Not be changed while bit 10 active or bit 15 run is set to
Context match register see .46 is ignored
 Isochronous receive context command pointer
Isochronous Receive Context Command Pointer Register
Isochronous receive context command pointer
−43
 Isochronous receive context match
Isochronous Receive Context Match Register
−35. Isochronous Receive Context Match Register Description
 Link Enhancement Control Set
DV and MPEG2 Timestamp Enhancements
−1. TI Extension Register Map
Link Enhancement Control Clear A8Ch
 Isochronous Receive Digital Video Enhancements Register
Isochronous Receive Digital Video Enhancements
Isochronous receive digital video enhancements
 CIPStrip1
Reserved. Bits 7 and 6 return 0s when read
420h/424h see .44 is cleared to
Ohci offset 420h/424h see .44 is cleared to
 Link enhancement
Reserved. Bit 11 returns 0 when read 10 ‡
Link Enhancement Register
−3. Link Enhancement Register Description
 Timestamp offset
Timestamp Offset Register
−4. Timestamp Offset Register Description
Page
 Address BIT Position
−1. Base Register Configuration
Base Registers
RHB IBR
 Field Size Type Description
−2. Base Register Field Descriptions
RHB
 Timeout
Long bus reset being performed
LLC to service the interrupt
Is unaffected by bus reset
 −4. Page 0 Port Status Register Field Descriptions
−3. Page 0 Port Status Register Configuration
Port Status Register
BIT Position Address
 Vendor Identification Register
−5. Page 1 Vendor ID Register Configuration
Hardware reset and is unaffected by bus reset
−6. Page 1 Vendor ID Register Field Descriptions
 −8. Page 7 Vendor-Dependent Register Field Descriptions
−7. Page 7 Vendor-Dependent Register Configuration
Vendor-Dependent Register
NPA
 Node does not need power and does not repeat power
Power-Class Programming
−9. Power Class Descriptions
PC0-PC2 Description
 10−8
 −1. Function 3 Configuration Register Map
Flash Media Controller Programming Model
 11−2
 Stepenb
 Pcispeed Devsel
 Storage controller
Programming interface. This field returns 00h when read
Is deasserted
 Flash media base address
Flash Media Base Address Register
−7. Flash Media Base Address Register Description
 Subsystem vendor identification
Subsystem Vendor Identification Register
Capabilities Pointer Register
Capabilities pointer
 Intsel Bits Useinta Intpin
−8. PCI Interrupt Pin Register
11−8
 Minimum Grant Register
Maximum Latency Register
 This field returns 00h when read
 −12. Power Management Capabilities Register Description
 Pmeen
Power Management Bridge Support Extension Register
Pmestat RCU
PME Rsvd
 Power management data
Power Management Data Register
−14. General Control Register
 SubsystemVendorID
−15. Subsystem Access Register Description
Register at PCI offset 2Ch 11−14
 Tbdctrl
−16. Diagnostic Register Description
Diagnostic
Plln
 11−16
 Slot information
−1. Function 4 Configuration Register Map
Maximum current
 12−2
 Transactions therefore, bit 4 returns 0 when read
Therefore, bit 9 returns 0 when read
Bit 5 returns 0 when read
Bit 3 returns 0 when read
 Syserr RCU
 DMA capabilities
Peripheral
12−5
 Read
Memory-read line, and memory-read multiple transactions
12−6
 −7. SD host Base Address Register Description
SD Host Base Address Register
SD host base address
Type
 12.12 Interrupt Line Register
12−8
 Space see Section 12−9
 −11. Maximum Latency Register Description
Slot Information Register
Register Maximum latency
Numberslots
 12−11
 Controller to generate PME
−13. Power Management Capabilities Register Description
Driver is able to use it
Revision 12−12
 Register
Power management bridge support extension
Enable. Enables Signaling
12−13
 Dmaen
−15. General Control Register
01 = Intb 10 = Intc 11 = Intd
Dmasupport bit of each SD host socket is
 Reserved. Bits 31−17 return 0s when read
−16. Subsystem Access Register Description
−17. Diagnostic Register Description
Register at PCI offset 2Ch
 Slot 1 3.3-V Maximum Current Register
Slot 0 3.3-V Maximum Current Register
Slot 2 3.3-V Maximum Current Register
 Slot 4 3.3-V Maximum Current Register
Slot 3 3.3-V Maximum Current Register
Slot 5 3.3-V Maximum Current Register
 12−18
 1Ch−28h
−1. Function 5 Configuration Register Map
60h−FCh
 13−2
 Intdis
Seren
 Intstat
Is enabled and the Smart Card controller has
Tabtsig RCU
13−4
 Offset 08h Type Read-only Default 0780 0000h
 Card is a multifunction device
Smart Card Base Address Register
Smart Card base address register
Smart Card base address register
 Smart Card base address register 1−4
Smart Card Base Address Register 1−4
13−7
 13.13 Interrupt Line Register
13−8
 −8. Minimum Grant Register Description
−7. PCI Interrupt Pin Register
Space see Section 13−9
 −9. Maximum Latency Register Description
13−10
 PMED2
−11. Power Management Capabilities Register Description
PMED3HOT
PMED1 PMED0 D2SUPPORT
 Dstate
PME Grst Rsvd
13−12
 −13. General Control Register
Gated to reduce power consumption
Pin = 01 = Intb pin = 10 = Intc pin = 11 = Intd pin =
 Subsystem ID alias
Subsystem ID Alias Register
Class Code Alias Register
−14. Subsystem ID Alias Register Description
 Smart Card configuration
Smart Card Configuration 1 Register
Smart Card configuration
13−15
 −15. Smart Card Configuration 1 Register Description
 Pwrupdelay
Smart Card Configuration 2 Register
−16. Smart Card Configuration 2 Register Description
Reserved. Bits 7−0 return 0s when read 13−17
 13−18
 Operation MIN NOM MAX Unit
Absolute Maximum Ratings Over Operating Temperature Ranges†
Recommended Operating Conditions see Note
Avdd VCC VDPLL15 VDPLL33 Vccp
 Recommended Operating Conditions
 TJ#
 Parameter Terminals Operation Test Conditions MIN MAX Unit
 14.4.3 Receiver
14.4.1 Device
14.4.2 Driver
Parameter Test Condition MIN MAX Unit
 Parameter Alternate Test Conditions MIN MAX Unit
Switching Characteristics for PHY Port Interface
Operating, Timing, and Switching Characteristics
Parameter Test Conditions MIN TYP MAX Unit
 Mechanical Information
 15−2
 Package Option Addendum