4.33 General-Purpose Event Enable Register

The general-purpose event enable register contains bits that are set to enable GPE signals. See Table 4−11 for a complete description of the register contents.

Bit

7

 

6

 

 

5

 

4

 

3

 

 

 

 

2

 

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

General-purpose event enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RW

RW

 

 

R

RW

 

 

RW

 

RW

 

RW

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

 

 

0

 

0

 

0

 

 

 

 

0

 

0

0

 

Register:

General-purpose event enable

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

89h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

Read-only, Read/Write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

00h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 4−11. General-Purpose Event Enable Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

SIGNAL

 

TYPE

 

 

 

 

 

 

 

 

 

 

 

 

FUNCTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7 ‡

PWR_EN

 

RW

Power change

GPE

enable. When this bit is set,

GPE

is signaled on PWR_STS events.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6 ‡

VPP12_EN

 

RW

12-V VPP

GPE

enable. When this bit is set,

GPE

is signaled on VPP12_STS events.

 

5

RSVD

 

R

Reserved. This bit returns 0 when read. A write has no effect.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4 ‡

GP4_EN

 

RW

GPI4

GPE

enable. When this bit is set,

GPE

is signaled on GP4_STS events.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3 ‡

GP3_EN

 

RW

GPI3

GPE

enable. When this bit is set,

GPE

is signaled on GP3_STS events.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2 ‡

GP2_EN

 

RW

GPI2

GPE

enable. When this bit is set,

GPE

is signaled on GP2_STS events.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 ‡

GP1_EN

 

RW

GPI1

GPE

enable. When this bit is set,

GPE

is signaled on GP1_STS events.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0 ‡

GP0_EN

 

RW

GPI0

GPE

enable. When this bit is set,

GPE

is signaled on GP0_STS events.

 

 

This bit is cleared only by the assertion of GRST.

4.34 General-Purpose Input Register

The general-purpose input register contains the logical value of the data input to the GPI terminals. See Table 4−12 for a complete description of the register contents.

Bit

7

 

6

 

5

 

4

3

 

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

General-purpose input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

R

 

R

 

RU

RU

 

RU

RU

RU

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

 

0

 

X

X

 

X

X

X

 

Register:

General-purpose input

 

 

 

 

 

 

 

Offset:

8Ah

 

 

 

 

 

 

 

 

 

 

Type:

Read/Update, Read-only

 

 

 

 

 

 

 

Default:

XXh

 

 

 

 

 

 

 

 

 

 

 

 

Table 4−12. General-Purpose Input Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

SIGNAL

 

TYPE

 

 

 

 

FUNCTION

 

 

 

 

 

 

 

 

 

 

7−5

RSVD

 

R

Reserved. These bits return 0s when read. Writes have no effect.

 

 

 

 

 

 

 

 

4

GPI4_DATA

 

RU

GPI4 data input. This bit represents the logical value of the data input from GPI4.

 

 

 

 

 

 

 

3

GPI3_DATA

 

RU

GPI3 data input. This bit represents the logical value of the data input from GPI3.

 

 

 

 

 

 

 

2

GPI2_DATA

 

RU

GPI2 data input. This bit represents the logical value of the data input from GPI2.

 

 

 

 

 

 

 

1

GPI1_DATA

 

RU

GPI1 data input. This bit represents the logical value of the data input from GPI1.

 

 

 

 

 

 

 

0

GPI0_DATA

 

RU

GPI0 data input. This bit represents the logical value of the data input from GPI0.

 

4−24

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Texas Instruments PCI7621, PCI7411, PCI7611, PCI7421 General-Purpose Event Enable Register, General-Purpose Input Register