Texas Instruments PCI7621 Interrupt Masks and Flags, 11. PC Card Interrupt Events and Description

Table 3−11. PC Card Interrupt Events and Description

CARD TYPE	EVENT	TYPE			SIGNAL			DESCRIPTION
							A transition on BVD1 indicates a change in the
			BVD1(STSCHG)//CSTSCHG
	Battery conditions						PC Card battery conditions.
		CSC
	(BVD1, BVD2)						A transition on BVD2 indicates a change in the
16-bit			BVD2(SPKR)//CAUDIO
							PC Card battery conditions.
memory
	Wait states						A transition on READY indicates a change in the
		CSC	READY(IREQ)//CINT				ability of the memory PC Card to accept or provide
	(READY)
							data.
	Change in card						The assertion of				indicates a status change
								STSCHG
16-bit I/O		CSC	BVD1(STSCHG)//CSTSCHG
	status (STSCHG)						on the PC Card.
16-bit I/O/	Interrupt request						The assertion of			indicates an interrupt request
								IREQ
		Functional	READY(IREQ)//CINT
UltraMedia	(IREQ)						from the PC Card.
	Change in card						The assertion of CSTSCHG indicates a status
		CSC	BVD1(STSCHG)//CSTSCHG
	status (CSTSCHG)						change on the PC Card.
CardBus
	Interrupt request						The assertion of CINT indicates an interrupt request
		Functional	READY(IREQ)//CINT
	(CINT)						from the PC Card.
							A transition on either
All PC Cards/									CD1//CCD1 or CD2//CCD2
	Card insertion			CD1//CCD1,
Smart Card		CSC					indicates an insertion or removal of a 16-bit or
	or removal			CD2//CCD2
adapters/							CardBus PC Card.
UltraMedia/	Power cycle	CSC				N/A	An interrupt is generated when a PC Card power-up
Flash Media	complete						cycle has completed.

The naming convention for PC Card signals describes the function for 16-bit memory, I/O cards, and CardBus. For example, READY(IREQ)//CINT includes READY for 16-bit memory cards, IREQ for 16-bit I/O cards, and CINT for CardBus cards. The 16-bit memory card signal name is first, with the I/O card signal name second, enclosed in parentheses. The CardBus signal name follows after a double slash (//).

The 1997 PC Card Standard describes the power-up sequence that must be followed by the PCI7x21/PCI7x11 controller when an insertion event occurs and the host requests that the socket VCC and VPP be powered. Upon completion of this power-up sequence, the PCI7x21/PCI7x11 interrupt scheme can be used to notify the host system (see Table 3−1 1), denoted by the power cycle complete event. This interrupt source is considered a PCI7x21/PCI7x11 internal event, because it depends on the completion of applying power to the socket rather than on a signal change at the PC Card interface.

3.7.2Interrupt Masks and Flags

Host software may individually mask (or disable) most of the potential interrupt sources listed in Table 3−11 by setting the appropriate bits in the PCI7x21/PCI7x11 controller. By individually masking the interrupt sources listed, software can control those events that cause a PCI7x21/PCI7x11 interrupt. Host software has some control over the system interrupt the PCI7x21/PCI7x11 controller asserts by programming the appropriate routing registers. The PCI7x21/PCI7x11 controller allows host software to route PC Card CSC and PC Card functional interrupts to separate system interrupts. Interrupt routing somewhat specific to the interrupt signaling method used is discussed in more detail in the following sections.

When an interrupt is signaled by the PCI7x21/PCI7x11 controller, the interrupt service routine must determine which of the events listed in Table 3−10 caused the interrupt. Internal registers in the PCI7x21/PCI7x11 controller provide flags that report the source of an interrupt. By reading these status bits, the interrupt service routine can determine the action to be taken.

Table 3−10 details the registers and bits associated with masking and reporting potential interrupts. All interrupts can be masked except the functional PC Card interrupts, and an interrupt status flag is available for all types of interrupts.

Notice that there is not a mask bit to stop the PCI7x21/PCI7x11 controller from passing PC Card functional interrupts through to the appropriate interrupt scheme. These interrupts are not valid until the card is properly powered, and there must never be a card interrupt that does not require service after proper initialization.

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