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Texas Instruments PCI7411, PCI7421, PCI7611, PCI7621 11.3 Command Register

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11−3

11.3 Command Register

The command register provides control over the PCI7x21/PCI7x11 interface to the PCI bus. All bit functions adhere

to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 11−2 for a

complete description of the register contents.

Bit 15 14 13 12 11 109876543210

Name Command

Type RRRRRRW RRW RRW RRW RRW RW R

Default 0000000000000000

Register: Command

Offset: 04h

Type: Read/Write, Read-only

Default: 0000h

Table 11−2. Command Register Description

BIT FIELD NAME TYPE DESCRIPTION

15−11 RSVD R Reserved. Bits 15−11 return 0s when read.

10 INT_DISABLE RW INTx disable. When set to 1, this bit disables the function from asserting interrupts on the INTx signals.

0 = INTx assertion is enabled (default)

1 = INTx assertion is disabled

9 FBB_ENB R Fast back-to-back enable. The flash media interface does not generate fast back-to-back transactions;

therefore, bit 9 returns 0 when read.

8 SERR_ENB RW SERR enable. When bit 8 is set to 1, the flash media interface SERR driver is enabled. SERR can be

asserted after detecting an address parity error on the PCI bus.

7 STEP_ENB R Address/data stepping control. The flash media interface does not support address/data stepping;

therefore, bit 7 is hardwired to 0.

6 PERR_ENB RW Parity error enable. When bit 6 is set to 1, the flash media interface is enabled to drive PERR response

to parity errors through the PERR signal.

5 VGA_ENB R VGA palette snoop enable. The flash media interface does not feature VGA palette snooping;

therefore, bit 5 returns 0 when read.

4 MWI_ENB RW Memory write and invalidate enable. The flash media controller does not generate memory write

invalidate transactions; therefore, bit 4 returns 0 when read.

3 SPECIAL R Special cycle enable. The flash media interface does not respond to special cycle transactions;

therefore, bit 3 returns 0 when read.

2 MASTER_ENB RW Bus master enable. When bit 2 is set to 1, the flash media interface is enabled to initiate cycles on the

PCI bus.

1 MEMORY_ENB RW Memory response enable. Setting bit 1 to 1 enables the flash media interface to respond to memory

cycles on the PCI bus.

0 IO_ENB R I/O space enable. The flash media interface does not implement any I/O-mapped functionality;

therefore, bit 0 returns 0 when read.

Contents

Main Page Contents Page Page Page Page Page Page Page Page List of Illustrations List of Tables Page Page Page Page Page 1 Introduction 1.1 Controller Functional Description 1.1.1 PCI7621 Controller 1.1.2 PCI7421 Controller 1.1.3 PCI7611 Controller 1.1.4 PCI7411 Controller 1.1.5 Multifunctional Terminals 1.1.6 PCI Bus Power Management 1.1.7 Power Switch Interface 1.2 Features 1.3 Related Documents 1.4 Trademarks 1.5 Terms and Definitions Terms and definitions used in this document are given in Table 11. Table 11. Terms and Definitions 1.6 Ordering Information Page 21 2 Terminal Descriptions Figure 21. PCI7621 GHK/ZHK-Package Terminal Diagram Figure 22. PCI7421 GHK/ZHK-Package Terminal Diagram 22 Figure 23. PCI7611 GHK/ZHK-Package Terminal Diagram 23 24 Table 21. Signal Names by GHK Terminal Number Page Page Page Table 22. CardBus PC Card Signal Names Sorted Alphabetically Table 22. CardBus PC Card Signal Names Sorted Alphabetically (Continued) Table 23. 16-Bit PC Card Signal Names Sorted Alphabetically Table 23. 16-Bit PC Card Signal Names Sorted Alphabetically (Continued) 2.1 Detailed Terminal Descriptions 214 215 216 217 218 219 220 221 Table 211. 16-Bit PC Card Interface Control Terminals (Continued) 222 223 224 225 Table 214. CardBus PC Card Interface Control Terminals (Continued) 226 Table 215. IEEE 1394 Physical Layer Terminals 227 228 229 These terminals are reserved for the PCI7421 and PCI7411 controllers. Page 3 Feature/Protocol Descriptions 3.1 Power Supply Sequencing 3.2 I/O Characteristics 3.3 Clamping Voltages 3.4 Peripheral Component Interconnect (PCI) Interface 3.4.1 1394 PCI Bus Master 3.4.2 Device Resets 3.4.3 Serial EEPROM I2C Bus 3.4.4 Functions 0 and 1 (CardBus) Subsystem Identification 3.4.5 Function 2 (OHCI 1394) Subsystem Identification 3.4.6 Function 3 (Flash Media) Subsystem Identification 3.4.7 Function 4 (SD Host) Subsystem Identification 3.4.8 Function 5 (Smart Card) Subsystem Identification 3.5 PC Card Applications 3.5.1 PC Card Insertion/Removal and Recognition 3.5.2 Low Voltage CardBus Card Detection 3.5.3 UltraMedia Card Detection 3.5.4 Flash Media Card Detection 3.5.5 Power Switch Interface Table 34. TPS2228 Control LogicxVCC Table 35. TPS2226 Control LogicxVPP Table 36. TPS2226 Control LogicxVCC 3.5.6 Internal Ring Oscillator 3.5.7 Integrated Pullup Resistors for PC Card Interface 3.5.8 SPKROUT and CAUDPWM Usage 3.5.9 LED Socket Activity Indicators 3.5.10 CardBus Socket Registers 3.5.11 48-MHz Clock Requirements 3.6 Serial EEPROM Interface 3.6.1 Serial-Bus Interface Implementation 3.6.2 Accessing Serial-Bus Devices Through Software 3.6.3 Serial-Bus Interface Protocol Page 3.6.4 Serial-Bus EEPROM Application Table 39. EEPROM Loading Map Table 39. EEPROM Loading Map (Continued) 3.7 Programmable Interrupt Subsystem 3.7.1 PC Card Functional and Card Status Change Interrupts 3.7.2 Interrupt Masks and Flags 3.7.3 Using Parallel IRQ Interrupts 3.7.4 Using Parallel PCI Interrupts 3.7.5 Using Serialized IRQSER Interrupts 3.7.6 SMI Support in the PCI7x21/PCI7x11 Controller 3.8 Power Management Overview 3.8.1 1394 Power Management (Function 2) 3.8.2 Integrated Low-Dropout Voltage Regulator (LDO-VR) 3.8.3 CardBus (Functions 0 and 1) Clock Run Protocol 3.8.4 CardBus PC Card Power Management 3.8.5 16-Bit PC Card Power Management 3.8.6 Suspend Mode 3.8.7 Requirements for Suspend Mode 3.8.8 Ring Indicate 3.8.9 PCI Power Management 3.8.9.1 CardBus Power Management (Functions 0 and 1) 3.8.9.2 OHCI 1394 (Function 2) Power Management 3.8.9.3 Flash Media (Function 3) Power Management 3.8.9.4 SD Host (Function 4) Power Management 3.8.9.5 Smart Card (Function 5) Power Management 3.8.10 CardBus Bridge Power Management 3.8.11 ACPI Support 3.8.12 Master List of PME Context Bits and Global Reset-Only Bits Page Page 3.9 IEEE 1394 Application Information 3.9.1 PHY Port Cable Connection Figure 318. Typical Compliant DC Isolated Outer Shield Termination Figure 317. TP Cable Connections 3.9.2 Crystal Selection 3.9.3 Bus Reset Page Page 4 PC Card Controller Programming Model 4.1 PCI Configuration Register Map (Functions 0 and 1) Table 42. Functions 0 and 1 PCI Configuration Register Map (Continued) 4.2 Vendor ID Register Default: 104Ch Register: Vendor ID Offset: 00h (Functions 0, 1) 4.3 Device ID Register Functions 0 and 1 4.4 Command Register 4.5 Status Register 4.6 Revision ID Register 4.7 Class Code Register 4.8 Cache Line Size Register 4.9 Latency Timer Register 4.10 Header Type Register 4.11 BIST Register 4.12 CardBus Socket Registers/ExCA Base Address Register 4.13 Capability Pointer Register 4.14 Secondary Status Register 4.15 PCI Bus Number Register 4.16 CardBus Bus Number Register 4.17 Subordinate Bus Number Register 4.18 CardBus Latency Timer Register 4.19 CardBus Memory Base Registers 0, 1 4.20 CardBus Memory Limit Registers 0, 1 4.21 CardBus I/O Base Registers 0, 1 4.22 CardBus I/O Limit Registers 0, 1 4.23 Interrupt Line Register 4.24 Interrupt Pin Register Register: Interrupt pin Offset: 3Dh 4.25 Bridge Control Register Register: Bridge control Offset: 3Eh (Function 0, 1) Default: 0340h Table 47. Bridge Control Register Description 4.26 Subsystem Vendor ID Register 4.27 Subsystem ID Register 4.28 PC Card 16-Bit I/F Legacy-Mode Base-Address Register 4.29 System Control Register Register: System control Offset: 80h (Functions 0, 1) Default: 0844 9060h Table 48. System Control Register Description Page Table 48.System Control Register Description (continued) 4.30 MC_CD Debounce Register Default: 19h Register: MC_CD debounce Offset: 84h (Functions 0, 1) 4.31 General Control Register Table 49. General Control Register Description 4.32 General-Purpose Event Status Register 4.33 General-Purpose Event Enable Register 4.34 General-Purpose Input Register 4.35 General-Purpose Output Register 4.36 Multifunction Routing Status Register Register: Multifunction routing status Offset: 8Ch Default: 0000 1000h Table 414. Multifunction Routing Status Register Description Table 414. Multifunction Routing Status Register Description (Continued) 4.37 Retry Status Register 4.38 Card Control Register 4.39 Device Control Register 4.40 Diagnostic Register 4.41 Capability ID Register 4.42 Next Item Pointer Register 4.43 Power Management Capabilities Register 4.44 Power Management Control/Status Register 4.45 Power Management Control/Status Bridge Support Extensions Register 4.46 Power-Management Data Register 4.47 Serial Bus Data Register 4.48 Serial Bus Index Register 4.49 Serial Bus Slave Address Register 4.50 Serial Bus Control/Status Register Register: Serial bus control/status Offset: B3h (function 0) Type: Read-only, Read/Write, Read/Clear Table 425. Serial Bus Control/Status Register Description Page 5 ExCA Compatibility Registers (Functions 0 and 1) Figure 51. ExCA Register Access Through I/O Figure 52. ExCA Register Access Through Memory Table 51. ExCA Registers and Offsets Table 51. ExCA Registers and Offsets (continued) 5.1 ExCA Identification and Revision Register 5.2 ExCA Interface Status Register Default: 00XX XXXXb Table 53. ExCA Interface Status Register Description 5.3 ExCA Power Control Register Table 54. ExCA Power Control Register Description82365SL Support Table 55. ExCA Power Control Register Description82365SL-DF Support 5.4 ExCA Interrupt and General Control Register Table 56. ExCA Interrupt and General Control Register Description 5.5 ExCA Card Status-Change Register 5.6 ExCA Card Status-Change Interrupt Configuration Register Table 58. ExCA Card Status-Change Interrupt Configuration Register Description 5.7 ExCA Address Window Enable Register 5.8 ExCA I/O Window Control Register Table 510. ExCA I/O Window Control Register Description 5.9 ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers 5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers 5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers 5.12 ExCA I/O Windows 0 and 1 End-Address High-Byte Registers 5.13 ExCA Memory Windows 04 Start-Address Low-Byte Registers 5.14 ExCA Memory Windows 04 Start-Address High-Byte Registers 5.15 ExCA Memory Windows 04 End-Address Low-Byte Registers 5.16 ExCA Memory Windows 04 End-Address High-Byte Registers 5.17 ExCA Memory Windows 04 Offset-Address Low-Byte Registers 5.18 ExCA Memory Windows 04 Offset-Address High-Byte Registers 5.19 ExCA Card Detect and General Control Register 5.20 ExCA Global Control Register 5.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers 5.22 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers 5.23 ExCA Memory Windows 04 Page Registers 6 CardBus Socket Registers (Functions 0 and 1) 6.1 Socket Event Register 6.2 Socket Mask Register 6.3 Socket Present State Register Table 64. Socket Present State Register Description (Continued) 6.4 Socket Force Event Register Table 65. Socket Force Event Register Description 6.5 Socket Control Register Register: Socket control Offset: CardBus Socket Address + 10h Default: 0000 0400h Table 66. Socket Control Register Description 6.6 Socket Power Management Register Register: Socket power management Offset: CardBus Socket Address + 20h Default: 0000 0000h Table 67. Socket Power Management Register Description 7 OHCI Controller Programming Model 7.1 Vendor ID Register 7.2 Device ID Register 7.3 Command Register 7.4 Status Register 7.5 Class Code and Revision ID Register 7.6 Latency Timer and Class Cache Line Size Register 7.7 Header Type and BIST Register 7.8 OHCI Base Address Register 7.9 TI Extension Base Address Register 7.10 CardBus CIS Base Address Register 7.11 CardBus CIS Pointer Register 7.12 Subsystem Identification Register 7.13 Power Management Capabilities Pointer Register 7.14 Interrupt Line Register 7.15 Interrupt Pin Register 7.16 Minimum Grant and Maximum Latency Register 7.17 OHCI Control Register 7.18 Capability ID and Next Item Pointer Registers 7.19 Power Management Capabilities Register Table 716. Power Management Capabilities Register Description 7.20 Power Management Control and Status Register 7.21 Power Management Extension Registers 7.22 PCI PHY Control Register 7.23 PCI Miscellaneous Configuration Register Register: PCI miscellaneous configuration Offset: F0h Default: 0000 0000h Table 720. PCI Miscellaneous Configuration Register Description Table 720. PCI Miscellaneous Configuration Register Description (Continued) 7.24 Link Enhancement Control Register Register: Link enhancement control Offset: F4h Default: 0000 1000h Table 721. Link Enhancement Control Register Description 7.25 Subsystem Access Register 7.26 GPIO Control Register Table 723. GPIO Control Register Description (Continued) 8 OHCI Registers Page Table 81. OHCI Register Map (Continued) 8.1 OHCI Version Register 8.2 GUID ROM Register 8.3 Asynchronous Transmit Retries Register 8.4 CSR Data Register 8.5 CSR Compare Register 8.6 CSR Control Register 8.7 Configuration ROM Header Register 8.8 Bus Identification Register 8.9 Bus Options Register Register: Bus options Offset: 20h Default: X0XX A0X2h Table 87. Bus Options Register Description 8.10 GUID High Register 8.11 GUID Low Register 8.12 Configuration ROM Mapping Register 8.13 Posted Write Address Low Register 8.14 Posted Write Address High Register 8.15 Vendor ID Register 8.16 Host Controller Control Register Table 811. Host Controller Control Register Description (Continued) 8.17 Self-ID Buffer Pointer Register Default: XXXX XX00h Register: Self-ID buffer pointer Offset: 64h 8.18 Self-ID Count Register 8.19 Isochronous Receive Channel Mask High Register 8.20 Isochronous Receive Channel Mask Low Register 8.21 Interrupt Event Register Table 815. Interrupt Event Register Description (Continued) 8.22 Interrupt Mask Register Table 816. Interrupt Mask Register Description (Continued) 8.23 Isochronous Transmit Interrupt Event Register 8.24 Isochronous Transmit Interrupt Mask Register 8.25 Isochronous Receive Interrupt Event Register 8.26 Isochronous Receive Interrupt Mask Register 8.27 Initial Bandwidth Available Register 8.28 Initial Channels Available High Register 8.29 Initial Channels Available Low Register 8.30 Fairness Control Register 8.31 Link Control Register 8.32 Node Identification Register 8.33 PHY Layer Control Register 8.34 Isochronous Cycle Timer Register 8.35 Asynchronous Request Filter High Register Table 827. Asynchronous Request Filter High Register Description (Continued) 8.36 Asynchronous Request Filter Low Register 8.37 Physical Request Filter High Register Table 829. Physical Request Filter High Register Description (Continued) 8.38 Physical Request Filter Low Register 8.39 Physical Upper Bound Register (Optional Register) 8.40 Asynchronous Context Control Register 8.41 Asynchronous Context Command Pointer Register 8.42 Isochronous Transmit Context Control Register 8.43 Isochronous Transmit Context Command Pointer Register 8.44 Isochronous Receive Context Control Register Table 834. Isochronous Receive Context Control Register Description (Continued) 8.45 Isochronous Receive Context Command Pointer Register 8.46 Isochronous Receive Context Match Register 9 TI Extension Registers 9.1 DV and MPEG2 Timestamp Enhancements 9.2 Isochronous Receive Digital Video Enhancements 9.3 Isochronous Receive Digital Video Enhancements Register Table 92. Isochronous Receive Digital Video Enhancements Register Description (Continued) 9.4 Link Enhancement Register 9.5 Timestamp Offset Register Page 10 PHY Register Configuration 10.1 Base Registers Table 102. Base Register Field Descriptions Table 102. Base Register Field Descriptions (Continued) 10.2 Port Status Register Table 104. Page 0 (Port Status) Register Field Descriptions 10.3 Vendor Identification Register 10.4 Vendor-Dependent Register Table 108. Page 7 (Vendor-Dependent) Register Field Descriptions 10.5 Power-Class Programming Page 11 Flash Media Controller Programming Model 11.1 Vendor ID Register 11.2 Device ID Register 11.3 Command Register 11.4 Status Register 11.5 Class Code and Revision ID Register 11.6 Latency Timer and Class Cache Line Size Register 11.7 Header Type and BIST Register 11.8 Flash Media Base Address Register 11.9 Subsystem Vendor Identification Register 11.10 Subsystem Identification Register 11.11 Capabilities Pointer Register 11.12 Interrupt Line Register 11.13 Interrupt Pin Register 11.14 Minimum Grant Register 11.15 Maximum Latency Register 11.16 Capability ID and Next Item Pointer Registers 11.17 Power Management Capabilities Register Table 1112. Power Management Capabilities Register Description 11.18 Power Management Control and Status Register 11.19 Power Management Bridge Support Extension Register 11.20 Power Management Data Register 11.21 General Control Register 11.22 Subsystem Access Register 11.23 Diagnostic Register Page 12 SD Host Controller Programming Model 12.1 Vendor ID Register 12.2 Device ID Register 12.3 Command Register 12.4 Status Register 12.5 Class Code and Revision ID Register 12.6 Latency Timer and Class Cache Line Size Register 12.7 Header Type and BIST Register 12.8 SD Host Base Address Register 12.9 Subsystem Vendor Identification Register 12.10 Subsystem Identification Register 12.11 Capabilities Pointer Register 12.12 Interrupt Line Register 12.13 Interrupt Pin Register 12.14 Minimum Grant Register 12.15 Maximum Latency Register 12.16 Slot Information Register 12.17 Capability ID and Next Item Pointer Registers 12.18 Power Management Capabilities Register 12.19 Power Management Control and Status Register 12.20 Power Management Bridge Support Extension Register 12.21 Power Management Data Register 12.22 General Control Register 12.23 Subsystem Access Register 12.24 Diagnostic Register 12.25 Slot 0 3.3-V Maximum Current Register 12.26 Slot 1 3.3-V Maximum Current Register 12.27 Slot 2 3.3-V Maximum Current Register 12.28 Slot 3 3.3-V Maximum Current Register 12.29 Slot 4 3.3-V Maximum Current Register 12.30 Slot 5 3.3-V Maximum Current Register Page 13 Smart Card Controller Programming Model 13.1 Vendor ID Register 13.2 Device ID Register 13.3 Command Register 13.4 Status Register 13.5 Class Code and Revision ID Register 13.6 Latency Timer and Class Cache Line Size Register 13.7 Header Type and BIST Register 13.8 Smart Card Base Address Register 0 13.9 Smart Card Base Address Register 14 13.10 Subsystem Vendor Identification Register 13.11 Subsystem Identification Register 13.12 Capabilities Pointer Register 13.13 Interrupt Line Register 13.14 Interrupt Pin Register 13.15 Minimum Grant Register 13.16 Maximum Latency Register 13.17 Capability ID and Next Item Pointer Registers 13.18 Power Management Capabilities Register Table 1311. Power Management Capabilities Register Description 13.19 Power Management Control and Status Register 13.20 Power Management Bridge Support Extension Register 13.21 Power Management Data Register 13.22 General Control Register 13.23 Subsystem ID Alias Register 13.24 Class Code Alias Register 13.25 Smart Card Configuration 1 Register Table 1315. Smart Card Configuration 1 Register Description 13.26 Smart Card Configuration 2 Register Page 14 Electrical Characteristics 14.1 Absolute Maximum Ratings Over Operating Temperature Ranges 14.2 Recommended Operating Conditions (see Note 3) Recommended Operating Conditions (continued) k Recommended Operating Conditions (continued) k 14.3 Electrical Characteristics Over Recommended Operating Conditions (unless otherwise noted) 14.4.1 Device 14.4.2 Driver Figure 141. Test Load Diagram 14.4.3 Receiver 14.6 Switching Characteristics for PHY Port Interface 14.7 Operating, Timing, and Switching Characteristics of XI 15 Mechanical Information GHK (S-PBGA-N288) PLASTIC BALL GRID ARRAY Page PACKAGING INFORMATION PACKAGE OPTION ADDENDUM