1. Ohci Register Map, Guid ROM Guidrom | Texas Instruments PCI7611

8 OHCI Registers

The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory-mapped into a 2K-byte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space (see Section 7.8). These registers are the primary interface for controlling the PCI7x21/PCI7x11 IEEE 1394 link function.

This section provides the register interface and bit descriptions. Several set/clear register pairs in this programming model are implemented to solve various issues with typical read-modify-write control registers. There are two addresses for a set/clear register: RegisterSet and RegisterClear. See Table 8−1 for a register listing. A 1 bit written to RegisterSet causes the corresponding bit in the set/clear register to be set to 1; a 0 bit leaves the corresponding bit unaffected. A 1 bit written to RegisterClear causes the corresponding bit in the set/clear register to be cleared; a 0 bit leaves the corresponding bit in the set/clear register unaffected.

Typically, a read from either RegisterSet or RegisterClear returns the contents of the set or clear register, respectively. However, sometimes reading the RegisterClear provides a masked version of the set or clear register. The interrupt event register is an example of this behavior.

Table 8−1. OHCI Register Map

DMA CONTEXT	REGISTER NAME	ABBREVIATION	OFFSET

—	OHCI version	Version	00h

	GUID ROM	GUID_ROM	04h

	Asynchronous transmit retries	ATRetries	08h

	CSR data	CSRData	0Ch

	CSR compare	CSRCompareData	10h

	CSR control	CSRControl	14h

	Configuration ROM header	ConfigROMhdr	18h

	Bus identification	BusID	1Ch

	Bus options ‡	BusOptions	20h

	GUID high ‡	GUIDHi	24h

	GUID low ‡	GUIDLo	28h

	Reserved	—	2Ch−30h

	Configuration ROM mapping	ConfigROMmap	34h

	Posted write address low	PostedWriteAddressLo	38h

	Posted write address high	PostedWriteAddressHi	3Ch

	Vendor ID	VendorID	40h

	Reserved	—	44h−4Ch

	Host controller control ‡	HCControlSet	50h

		HCControlClr	54h
		HCControlClr	54h

	Reserved	—	58h−5Ch

‡One or more bits in this register are cleared only by the assertion of GRST.

8−1

Image 181

Texas Instruments PCI7611, PCI7411 1. Ohci Register Map, DMA Context Register Name Abbreviation Offset, Guid ROM Guidrom

Contents

Data Manual Important Notice Contents −10 PC Card Controller Programming Model −1 ExCA Compatibility Registers Functions 0 and 1 −1 Ohci Registers −1 Ohci Controller Programming Model −1Vii TI Extension Registers −1 PHY Register Configuration 10−1Viii SD Host Controller Programming Model −1 Flash Media Controller Programming Model −1 Smart Card Controller Programming Model −1 Mechanical Information 15−1 Electrical Characteristics −1 Xii List of Illustrations Xiii List of Tables Xiv Functions 0 and 1 PCI Configuration Register Map Title −13 Xvi Xvii Xviii 1 PCI7621 Controller Controller Functional Description 3 PCI7611 Controller 2 PCI7421 Controller Power Switch Interface PCI Bus Power Management4 PCI7411 Controller Multifunctional Terminals PCI Bus Interface Specification for PCI-to-CardBus Bridges Features Related Documents PCI Local Bus Specification Revision Trademarks Ordering Information Terms and Definitions−1. Terms and Definitions Term DefinitionsPage Terminal Descriptions −2. PCI7421 GHK/ZHK-Package Terminal Diagram −3. PCI7611 GHK/ZHK-Package Terminal Diagram −4. PCI7411 GHK/ZHK-Package Terminal Diagram Terminal Signal Name Number −1. Signal Names by GHK Terminal Number ACC/BE2 BresetVCC VCC Acperr BCC/BE0 BCE1 ScclkSCVCC5V Latch GNT Perr Grst FrameRIOUT/PME Vsspll Signal Name Terminal Number −2. CardBus PC Card Signal Names Sorted Alphabetically PC2TEST3 SdcmdPerr Trdy GND Prst GND Signal Terminal Signal Name Number −3 -Bit PC Card Signal Names Sorted Alphabetically −12 −13 Detailed Terminal Descriptions −14 −4. Power Supply Terminals −6. PCI System Terminals −5. PC Card Power Switch Terminals−15 −16 −7. PCI Address and Data Terminals −17 −8. PCI Interface Control Terminals −18 −9. Multifunction and Miscellaneous Terminals −10 -Bit PC Card Address and Data Terminals Stschg −11 -Bit PC Card Interface Control Terminals AOE PCIO3 Vccb −12. CardBus PC Card Interface System Terminals BCAD0 −13. CardBus PC Card Address and Data Terminals BCCD2 −14. CardBus PC Card Interface Control Terminals Cstop −26 −15. Ieee 1394 Physical Layer Terminals −17. Memory Stick/PRO Terminals −16. SD/MMC Terminals−27 −28 −18. Smart Media/XD Terminals −19. Smart Card Terminals † −30 Eeprom Power Supply SequencingSD/MMC MS/MSPRO SD/MMC Clamping Voltages I/O CharacteristicsPeripheral Component Interconnect PCI Interface 1 1394 PCI Bus Master Serial Eeprom I2C Bus Device ResetsVCC Grst Prst Pclk ROM A1 SCL A2 SDA VCC Functions 0 and 1 CardBus Subsystem Identification Function 2 Ohci 1394 Subsystem Identification PC Card ApplicationsFunction 3 Flash Media Subsystem Identification Function 4 SD Host Subsystem Identification Low Voltage CardBus Card Detection PC Card Insertion/Removal and RecognitionUltraMedia Card Detection −2. PC Card-Card Detect and Voltage Sense Connections Flash Media Card DetectionCD2//CCD2 CD1//CCD1 VS2//CVS2 VS1//CVS1 VCC VPP/VCORE −3. TPS2228 Control Logic-xVPP/VCORE Internal Ring Oscillator−4. TPS2228 Control Logic-xVCC −5. TPS2226 Control Logic-xVPP Integrated Pullup Resistors for PC Card Interface LED Socket Activity IndicatorsSpkrout and Caudpwm Usage Spkrout Binaryspkr 11 48-MHz Clock Requirements CardBus Socket Registers−7. CardBus Socket Registers LED Serial Eeprom Interface Accessing Serial-Bus Devices Through SoftwareSerial-Bus Interface Implementation Serial-Bus Interface Protocol −8. Serial-Bus Protocol Acknowledge −7. Serial-Bus Start/Stop Conditions and Bit Transfers −10. Serial-Bus Protocol-Byte Read Serial-Bus Eeprom Application Serial ROM Byte Description Offset −9. Eeprom Loading MapGPE PCI 2Ch, subsystem vendor ID, byte LinkEnh HCControl.Program Phy EnablePCI 2Dh, subsystem vendor ID, byte PCI 2Eh, subsystem ID, byte Programmable Interrupt Subsystem −10. Interrupt Mask and Flag Registers PC Card Functional and Card Status Change InterruptsCard Type Event Mask Flag Interrupt Masks and Flags Card Type Event Signal Description−11. PC Card Interrupt Events and Description Using Parallel PCI Interrupts Using Parallel IRQ Interrupts Using Serialized Irqser Interrupts Power Management OverviewSMI Support in the PCI7x21/PCI7x11 Controller −12. Interrupt Pin Register Cross Reference 1 1394 Power Management Function Integrated Low-Dropout Voltage Regulator LDO-VR CardBus PC Card Power ManagementCardBus Functions 0 and 1 Clock Run Protocol Supply VCC Vren Vrport Suspend Mode 5 16-Bit PC Card Power ManagementRequirements for Suspend Mode Reset GNT Suspend Pclk Cstsmask CSC Ringen RI Cdresume Ring IndicateRienb Riout −15. Power-Management Registers PCI Power ManagementPower-management control/status CSR −16. Function 2 Power-Management Registers CardBus Bridge Power Management−17. Function 3 Power-Management Registers −18. Function 4 Power-Management Registers Acpi Support Master List of PME Context Bits and Global Reset-Only Bits −28 −29 PHY Port Cable Connection Ieee 1394 Application Information −31 Crystal Selection Cphy + CBD Bus Reset−32 −33 −34 −1. Bit Field Access Tag Descriptions PCI Configuration Register Map Functions 0−2. Functions 0 and 1 PCI Configuration Register Map Access TAG Name Meaning Vendor ID Vendor ID Register Device ID Register Functions 0 Device ID-Smart Card enabledDevice ID Command Command Register−3. Command Register Description BIT Signal Type Function Status Status Register−4. Status Register Description Class Code Register Revision ID RegisterCache Line Size Register Register Latency timer Latency Timer RegisterHeader Type Register Bist Register Capability Pointer Register CardBus Socket Registers/ExCA Base Address RegisterCardBus socket registers/ExCA base address Register Capability pointer Secondary status Secondary Status Register−5. Secondary Status Register Description CardBus Bus Number Register PCI Bus Number RegisterSubordinate Bus Number Register Register CardBus latency timer CardBus Latency Timer RegisterCardBus Memory Base Registers 0 Memory base registers 0 CardBus I/O Base Registers 0 CardBus Memory Limit Registers 0Memory limit registers 0 Base registers 0 Interrupt Line Register CardBus I/O Limit Registers 0Limit registers 0 Register Interrupt line Interrupt pin − PCI function Interrupt Pin Register Interrupt pin Bridge Control Register−6. Interrupt Pin Register Cross Reference Bridge control Subsystem vendor ID Subsystem Vendor ID Register PC Card 16-Bit I/F Legacy-Mode Base-Address Register Subsystem ID RegisterSubsystem ID PC Card 16-bit I/F legacy-mode base-address System control System Control Register−8. System Control Register Description −8 . System Control Register Description Register Mccd debounce Mccd Debounce Register General control General Control RegisterGeneral control −9. General Control Register Description General-purpose event status General-Purpose Event Status Register−10. General-Purpose Event Status Register Description General-Purpose Input Register General-Purpose Event Enable Register General-purpose output General-Purpose Output Register−13. General-Purpose Output Register Description Multifunction routing status Multifunction Routing Status Register−14. Multifunction Routing Status Register Description Retry status Retry Status Register−15. Retry Status Register Description Card control Card Control Register−16. Card Control Register Description Device control Device Control Register−17. Device Control Register Description Diagnostic Diagnostic Register−18. Diagnostic Register Description Next Item Pointer Register Capability ID RegisterRegister Capability ID Register Next item pointer Power management capabilities Power Management Capabilities Register−19. Power Management Capabilities Register Description Power management control/status Power Management Control/Status Register−20. Power Management Control/Status Register Description Power management control/status bridge support extensions Power-Management Data RegisterPower-management data Bpccen Serial Bus Index Register Serial Bus Data RegisterSerial bus data −22. Serial Bus Data Register Description Register Serial bus slave address Serial Bus Slave Address Register−24. Serial Bus Slave Address Register Description Rwcmd Serial bus control/status Serial Bus Control/Status Register−25. Serial Bus Control/Status Register Description −38 ExCA Compatibility Registers Functions 0 −1. ExCA Register Access Through I/O −1. ExCA Registers and Offsets Exca Register Name PCI Memory Address Exca Offset Offset HEX ExCA identification and revision ExCA Identification and Revision Register−2. ExCA Identification and Revision Register Description Iftype ExCA interface status ExCA Interface Status Register−3. ExCA Interface Status Register Description ExCA power control ExCA Power Control Register−4. ExCA Power Control Register Description-82365SL Support Register ExCA interrupt and general control ExCA Interrupt and General Control Register−6. ExCA Interrupt and General Control Register Description ExCA card status-change ExCA Card Status-Change Register−7. ExCA Card Status-Change Register Description Register ExCA card status-change interrupt configuration ExCA Card Status-Change Interrupt Configuration Register ExCA address window enable ExCA Address Window Enable Register−9. ExCA Address Window Enable Register Description ExCA I/O window control ExCA I/O Window Control Register−10. ExCA I/O Window Control Register Description ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers ExCA I/O Windows 0 and 1 End-Address High-Byte Registers ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers ExCA Memory Windows 0−4 Start-Address Low-Byte Registers ExCA Memory Windows 0−4 Start-Address High-Byte Registers ExCA Memory Windows 0−4 End-Address Low-Byte Registers ExCA Memory Windows 0−4 End-Address High-Byte Registers ExCA Memory Windows 0−4 Offset-Address Low-Byte Registers ExCA Memory Windows 0−4 Offset-Address High-Byte Registers ExCA card detect and general control ExCA Card Detect and General Control Register ExCA global control ExCA Global Control Register−15. ExCA Global Control Register Description ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers Register ExCA memory windows 0−4 ExCA Memory Windows 0−4 Page Registers CardBus Socket Registers Functions 0 Socket event Socket Event Register−2. Socket Event Register Description Socket mask Socket Mask Register−3. Socket Mask Register Description Socket present state Socket Present State Register−4. Socket Present State Register Description Socket force event Socket Force Event Register −5. Socket Force Event Register Description Socket control Socket Control Register−6. Socket Control Register Description Socket power management Socket Power Management Register−7. Socket Power Management Register Description Pmcsrbse −1. Function 2 Configuration Register Map Device ID Register BIT Field Name Type Description −2. Command Register Description −3. Status Register Description Latency timer and class cache line size Latency Timer and Class Cache Line Size RegisterClass Code and Revision ID Register Class code and revision ID Ohci Base Address Register Header Type and Bist Register TI extension base address TI Extension Base Address Register−8. TI Base Address Register Description CardBus CIS Pointer Register CardBus CIS Base Address RegisterCardBus CIS base address −9. CardBus CIS Base Address Register Description Power management capabilities pointer Power Management Capabilities Pointer RegisterSubsystem Identification Register Subsystem identification Register Interrupt pin −11. Interrupt Line Register DescriptionBIT Field Name Type Description Intrline 01h Inta 02h Intb 03h Intc Bits Intsel Ohci Control Register Minimum Grant and Maximum Latency Register Capability ID and next item pointer Capability ID and Next Item Pointer RegistersNextitem Capabilityid −16. Power Management Capabilities Register Description Power Management Extension Registers Power Management Control and Status RegisterPower management control and status Power management extension PCI PHY control PCI PHY Control Register−19. PCI PHY Control Register Description Cnaout PCI miscellaneous configuration PCI Miscellaneous Configuration Register−20. PCI Miscellaneous Configuration Register Description Link enhancement control Link Enhancement Control Register−21. Link Enhancement Control Register Description Subsystem access Subsystem Access Register−22. Subsystem Access Register Description Subdevid Gpio control Gpio Control Register−23. Gpio Control Register Description GPIOENB1 GPIO1 Disablebmc GPIO0GPIODATA1 = GPIO0 DMA Context Register Name Abbreviation Offset −1. Ohci Register MapGuid ROM Guidrom Isochronous receive interrupt mask IsoRecvIntMaskSet IsoRecvIntEventClearPhysicalRequestFilterHiClear Physical request filter low PhysicalRequestFilterLoSet Asynchronous context control ContextControlSet Isochronous receive context commandContextControlClear Request Transmit Reserved Ohci version Ohci Version Register−2. Ohci Version Register Description −3. Guid ROM Register Description Guid ROM RegisterGuid ROM RSU CSR Data Register Asynchronous Transmit Retries RegisterAsynchronous transmit retries −4. Asynchronous Transmit Retries Register Description CSR Control Register CSR Compare RegisterCSR compare CSR control Configuration ROM header Configuration ROM Header Register−6. Configuration ROM Header Register Description Bus Identification Register Bus options Bus Options Register−7. Bus Options Register Description Guid Low Register Guid High RegisterGuid high Guid low Posted Write Address Low Register Configuration ROM Mapping Register Posted write address high Posted Write Address High Register−10. Posted Write Address High Register Description Host controller control Host Controller Control Register−11. Host Controller Control Register Description RSU RSC Rscu Self-ID buffer pointer Self-ID Buffer Pointer RegisterLPS RSC Self-ID count Self-ID Count Register−12. Self-ID Count Register Description Isochronous receive channel mask high Isochronous Receive Channel Mask High Register Isochronous receive channel mask low Isochronous Receive Channel Mask Low Register Interrupt event Interrupt Event Register−15. Interrupt Event Register Description RSC Rscu Arrq Rscu Arrs Rscu Interrupt Mask Register MasterIntEnableInterrupt mask −16. Interrupt Mask Register Description Arrq RSC Arrs RSCGeneration Isochronous transmit interrupt event Isochronous Transmit Interrupt Event Register Isochronous transmit interrupt mask Isochronous Transmit Interrupt Mask Register Isochronous Receive Interrupt Event Register Reserved. Bits 31−4 return 0s when readIsochronous receive interrupt event Initial Bandwidth Available Register Isochronous Receive Interrupt Mask RegisterIsochronous receive interrupt mask Initial bandwidth available Initial Channels Available Low Register Initial Channels Available High Register Fairness control Fairness Control Register−22. Fairness Control Register Description Value for this field is 00h Link control Link Control Register−23. Link Control Register Description Node identification Node Identification Register−24. Node Identification Register Description PHY layer control PHY Layer Control Register−25. PHY Control Register Description Isochronous cycle timer Isochronous Cycle Timer Register−26. Isochronous Cycle Timer Register Description Asynchronous request filter high Asynchronous Request Filter High Register−27. Asynchronous Request Filter High Register Description From that node are accepted Asynchronous request filter low Asynchronous Request Filter Low Register−28. Asynchronous Request Filter Low Register Description Physical request filter high Physical Request Filter High Register−29. Physical Request Filter High Register Description PhysReqAllBusses That node are handled through the physical request context Physical Upper Bound Register Optional Register Physical Request Filter Low RegisterPhysical request filter low −30. Physical Request Filter Low Register Description Asynchronous context control Asynchronous Context Control Register−31. Asynchronous Context Control Register Description Rscu RSU Asynchronous context command pointer Asynchronous Context Command Pointer RegisterDescriptorAddress Isochronous transmit context control Isochronous Transmit Context Control RegisterRSC RSU Isochronous transmit context command pointer Isochronous Transmit Context Command Pointer RegisterIsochronous Receive Context Control Register Isochronous receive context control Not be changed while bit 10 active or bit 15 run is set to When software clears bit 15 runMultiChanMode Context match register see .46 is ignored Isochronous receive context command pointer Isochronous Receive Context Command Pointer RegisterIsochronous receive context command pointer −43 Isochronous receive context match Isochronous Receive Context Match Register−35. Isochronous Receive Context Match Register Description −1. TI Extension Register Map DV and MPEG2 Timestamp EnhancementsLink Enhancement Control Set Link Enhancement Control Clear A8Ch Isochronous Receive Digital Video Enhancements Register Isochronous Receive Digital Video EnhancementsIsochronous receive digital video enhancements 420h/424h see .44 is cleared to Reserved. Bits 7 and 6 return 0s when readCIPStrip1 Ohci offset 420h/424h see .44 is cleared to Link Enhancement Register Reserved. Bit 11 returns 0 when read 10 ‡Link enhancement −3. Link Enhancement Register Description Timestamp offset Timestamp Offset Register−4. Timestamp Offset Register Description Page Base Registers −1. Base Register ConfigurationAddress BIT Position RHB IBR Field Size Type Description −2. Base Register Field DescriptionsRHB LLC to service the interrupt Long bus reset being performedTimeout Is unaffected by bus reset Port Status Register −3. Page 0 Port Status Register Configuration−4. Page 0 Port Status Register Field Descriptions BIT Position Address Hardware reset and is unaffected by bus reset −5. Page 1 Vendor ID Register ConfigurationVendor Identification Register −6. Page 1 Vendor ID Register Field Descriptions Vendor-Dependent Register −7. Page 7 Vendor-Dependent Register Configuration−8. Page 7 Vendor-Dependent Register Field Descriptions NPA −9. Power Class Descriptions Power-Class ProgrammingNode does not need power and does not repeat power PC0-PC2 Description 10−8 Flash Media Controller Programming Model −1. Function 3 Configuration Register Map 11−2 Stepenb Pcispeed Devsel Storage controller Programming interface. This field returns 00h when readIs deasserted Flash media base address Flash Media Base Address Register−7. Flash Media Base Address Register Description Capabilities Pointer Register Subsystem Vendor Identification RegisterSubsystem vendor identification Capabilities pointer Intsel Bits Useinta Intpin −8. PCI Interrupt Pin Register11−8 Maximum Latency Register Minimum Grant Register This field returns 00h when read −12. Power Management Capabilities Register Description Pmestat RCU Power Management Bridge Support Extension RegisterPmeen PME Rsvd Power management data Power Management Data Register−14. General Control Register SubsystemVendorID −15. Subsystem Access Register DescriptionRegister at PCI offset 2Ch 11−14 Diagnostic −16. Diagnostic Register DescriptionTbdctrl Plln 11−16 Slot information −1. Function 4 Configuration Register MapMaximum current 12−2 Bit 5 returns 0 when read Therefore, bit 9 returns 0 when readTransactions therefore, bit 4 returns 0 when read Bit 3 returns 0 when read Syserr RCU DMA capabilities Peripheral12−5 Read Memory-read line, and memory-read multiple transactions12−6 SD host base address SD Host Base Address Register−7. SD host Base Address Register Description Type 12−8 12.12 Interrupt Line Register Space see Section 12−9 Register Maximum latency Slot Information Register−11. Maximum Latency Register Description Numberslots 12−11 Driver is able to use it −13. Power Management Capabilities Register DescriptionController to generate PME Revision 12−12 Enable. Enables Signaling Power management bridge support extensionRegister 12−13 01 = Intb 10 = Intc 11 = Intd −15. General Control RegisterDmaen Dmasupport bit of each SD host socket is −17. Diagnostic Register Description −16. Subsystem Access Register DescriptionReserved. Bits 31−17 return 0s when read Register at PCI offset 2Ch Slot 1 3.3-V Maximum Current Register Slot 0 3.3-V Maximum Current RegisterSlot 2 3.3-V Maximum Current Register Slot 4 3.3-V Maximum Current Register Slot 3 3.3-V Maximum Current RegisterSlot 5 3.3-V Maximum Current Register 12−18 1Ch−28h −1. Function 5 Configuration Register Map60h−FCh 13−2 Seren Intdis Tabtsig RCU Is enabled and the Smart Card controller hasIntstat 13−4 Offset 08h Type Read-only Default 0780 0000h Smart Card base address register Smart Card Base Address RegisterCard is a multifunction device Smart Card base address register Smart Card base address register 1−4 Smart Card Base Address Register 1−413−7 13−8 13.13 Interrupt Line Register −8. Minimum Grant Register Description −7. PCI Interrupt Pin RegisterSpace see Section 13−9 13−10 −9. Maximum Latency Register Description PMED3HOT −11. Power Management Capabilities Register DescriptionPMED2 PMED1 PMED0 D2SUPPORT Dstate PME Grst Rsvd13−12 −13. General Control Register Gated to reduce power consumptionPin = 01 = Intb pin = 10 = Intc pin = 11 = Intd pin = Class Code Alias Register Subsystem ID Alias RegisterSubsystem ID alias −14. Subsystem ID Alias Register Description Smart Card configuration Smart Card Configuration 1 RegisterSmart Card configuration 13−15 −15. Smart Card Configuration 1 Register Description −16. Smart Card Configuration 2 Register Description Smart Card Configuration 2 RegisterPwrupdelay Reserved. Bits 7−0 return 0s when read 13−17 13−18 Recommended Operating Conditions see Note Absolute Maximum Ratings Over Operating Temperature Ranges†Operation MIN NOM MAX Unit Avdd VCC VDPLL15 VDPLL33 Vccp Recommended Operating Conditions TJ# Parameter Terminals Operation Test Conditions MIN MAX Unit 14.4.2 Driver 14.4.1 Device14.4.3 Receiver Parameter Test Condition MIN MAX Unit Operating, Timing, and Switching Characteristics Switching Characteristics for PHY Port InterfaceParameter Alternate Test Conditions MIN MAX Unit Parameter Test Conditions MIN TYP MAX Unit Mechanical Information 15−2 Package Option Addendum