Texas Instruments PCI7421, PCI7411, PCI7611, PCI7621 manual Terminal Descriptions

2 Terminal Descriptions

The PCI7x21/PCI7x11 controller is available in the 288-terminal MicroStar BGA package (GHK) or the 288-terminal lead-free (Pb, atomic number 82) MicroStar BGA package (ZHK). Figure 2−1 is a pin diagram of the PCI7621 package. Figure 2−2 is a pin diagram of the PCI7421 package. Figure 2−3 is a pin diagram of the PCI7611 package. Figure 2−4 is a pin diagram of the PCI7411 package.

W

AD27

VCCP

C/BE3

IDSEL

AD19

C/BE2

STOP

C/BE1

VCCP

C/BE0

AD4

AD0

TPB0N

TPA0N

TPB1N

NC

TPA1N

V

AD30

AD29

AD26

AD24

AD23

AD18

FRAME

PERR

AD15

AD11

AD7

AD3

PC2

TPB0P

TPA0P

TPB1P

AVDD

TPA1P

VDPLL_

(TEST3)

33

U

REQ

AD31

AD28

AD25

AD22

AD17

IRDY

SERR

AD14

AD10

AD6

AD2

PC1

AGND

TPBIAS0

AGND

TPBIAS1

R0

R1

(TEST2)

T

GRST

GNT

RI_OUT

VSSPLL

VDPLL_

RSVD

//PME

15

R

PC0

PHY_

XI

MFUNC6 SUSPEND

PRST

AD21

AD16

TRDY

AD13

AD9

AD5

AVDD

AVDD

TEST_

XO

(TEST1)

MA

P

MFUNC2 MFUNC3 MFUNC4

PCLK

AD20

PAR

TEST0

VSSPLL

CNA

B_CAD1

B_CAD2

B_CAD0

//B_D4

//B_D11

//B_D3

N

DATA

LATCH MFUNC0

MFUNC5

VCC

DEVSEL

AD12

AD8

AD1

AGND

B_CCD1

B_CAD4

B_RSVD

B_CAD5

B_CAD6

//B_CD1

//B_D12

//B_D14

//B_D6

//B_D13

M

CLK_48

SDA

SCL

MFUNC1

VCC

GND

VCC

VCC

CPS

VCC

B_CAD3

B_CAD8

B_CAD7

B_CAD9

B_CC/BE0

VR_

//B_D5

//B_D15

//B_D7

//B_A10

//B_CE1

PORT

L

SC_

SC_

B_CAD15

B_CAD13

B_CAD12

B_CAD11 B_CAD10

SC_CD

SC_OC

PWR_

CLOCK SPKROUT

GND

GND

GND

GND

GND

DATA

//B_IOWR

//B_IORD

//B_A11

//B_OE

//B_CE2

CTRL

K

SM_R/B//

SM_PHYS

SC_VCC

GND

B_CPAR

B_CC/BE1 B_RSVD

B_CAD16 B_CAD14

_WP//

SC_RST

SC_CLK

VCC

GND

GND

VCC

VCCB

//B_A13

//B_A8

//B_A18

SC_RFU

SC_FCB

_5V

//B_A17

//B_A9

J

SD_DAT2 SD_DAT3

SD_CMD//

SD_CLK// SD_DAT1// SM_CLE//

VCC

GND

GND

GND

VCC

B_CIRDY

B_CGNT

B_CSTOP B_CPERR

B_CBLOCK

//SM_D6//

//SM_D7//

SM_ALE//

SM_RE//

SM_D5//

//B_A15

//B_WE

//B_A20

//B_A14

//B_A19

SC_GPIO4

SC_GPIO3 SC_GPIO2

SC_GPIO1 SC_GPIO5 SC_GPIO0

H

VR_

SD_DAT0//

MS_DATA3//

SD_WP//

VCC

VCC

B_CAD19

B_CAD18

B_CTRDY B_CCLK

B_CDEVSEL

VR_EN

SM_D4//

SD_DAT3

VCC

VCC

VCC

GND

PORT

SM_CE

//B_A25

//B_A7

//B_A22

//B_A16

//B_A21

//SM_D3

SC_GPIO6

G

MS_SDIO

MS_DATA1 MS_DATA2

MS_CLK//

A_CAD20

A_CPAR

A_CAD14 A_CC/BE0

B_CAD21

B_CAD17 B_CC/BE2B_CFRAME

(DATA0)//

//SD_DAT1

//SD_DAT2

SD_CLK//

GND

GND

GND

//B_A24

//B_A12

//B_A23

SD_DAT0//

//SM_D1

//SM_D2

SM_EL_WP

//A_A6

//A_A13

//A_A9

//A_CE1

//B_A5

SM_D0

F

MC_PWR MC_PWR

MS_BS//

MS_CD

SM_CD

A_CC/BE2

A_CPERR

A_CAD6

B_CSTSCHG B_CC/BE3

B_CRST

B_CAD20 B_CVS2

_CTRL_0

_CTRL_1

SD_CMD

//A_A12

//A_A14

//A_D13

//B_BVD1

//B_REG

//B_RESET

//B_A6

//B_VS2

//SM_WE

(STSCHG/RI)

E

B_USB_EN A_USB_EN

SD_CD

A_CCD2 A_CAD24

A_CREQ

A_CVS2

A_CCLK

A_CBLOCK A_CAD15

A_CAD8

A_CAD3 A_CAD0

B_CAD23

B_CREQ B_CAD22

//A_CD2

//A_A2

//A_INPACK

//A_VS2

//A_A16

//A_A19

//A_IOWR

//A_D15

//A_D5

//A_D3

//B_A3

//B_INPACK

//B_A4

D

A_CAD31

A_RSVD

A_CAD29

B_CAD26 B_CAD24

VCCB

//A_D10

//A_D2

//A_D1

//B_A0

//B_A2

C

A_CAD30

A_CAD28

A_CCLKRUN A_CINT//

A_CC/BE3 A_CAD22 A_CAD19 A_CFRAME A_CDEVSEL

A_RSVD

A_CAD13 A_CAD11

A_CAD7

A_CAD4

A_CCD1

B_CAD27

B_CAUDIO

B_CVS1 B_CAD25

//A_WP A_READY

//B_BVD2

//A_D9

//A_D8

(IOIS16)

(IREQ)

//A_REG

//A_A4

//A_A25

//A_A23

//A_A21

//A_A18

//A_IORD

//A_OE

//A_D7

//A_D12

//A_CD1

//B_D0

(SPKR)

//B_VS1

//B_A1

B

A_CAD27

A_CSTSCHG

A_CSERR A_CAD26

A_CAD23 A_CAD21 A_CAD18

A_CIRDY

A_CGNT A_CC/BE1 A_CAD12 A_CAD10

A_RSVD

A_CAD1 B_CAD31 B_CAD29 B_CCD2

B_CINT

//A_BVD1

B_CSERR //B_READY

//A_D0

(STSCHG/RI)

//A_WAIT

//A_A0

//A_A3

//A_A5

//A_A7

//A_A15

//A_WE

//A_A8

//A_A11

//A_CE2

//A_D14

//A_D4

//B_D10

//B_D1

//B_CD2

//B_WAIT

(IREQ)

A

A_CAUDIO

A_CVS1

A_CAD25

VCCA

A_CRST

A_CAD17 A_CTRDY A_CSTOP A_CAD16

A_CAD9

A_CAD5

A_CAD2

B_RSVD

B_CAD30 B_CAD28 B_CCLKRUN

//A_BVD2

//A_VS1

//A_A1

//A_RESET

//A_A24

//A_A22

//A_A20

//A_A17

VCCA

//A_A10

//A_D6

//A_D11

//B_D2

//B_D9

//B_D8

//B_WP

(IOIS16)

(SPKR)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

Figure 2−1. PCI7621 GHK/ZHK-Package Terminal Diagram

2−1