Texas Instruments PCI7421, PCI7411, PCI7611, PCI7621 manual 8. PCI Interface Control Terminals, 17

Table 2−8. PCI Interface Control Terminals

Internal pullup/pulldown resistors and pin strapping are not applicable for the PCI interface control terminals.

TERMINAL

DESCRIPTION

I/O

INPUT

OUTPUT

POWER

EXTERNAL

NAME

NO.

TYPE

RAIL

COMPONENTS

PCI device select. The controller asserts

to claim a PCI cycle

DEVSEL

N08

as the target device. As a PCI initiator on the bus, the controller monitors

I/O

PCII3

PCIO3

VCCP

Pullup resistor per

DEVSEL

DEVSEL until a target responds. If no target responds before timeout

PCI specification

occurs, then the controller terminates the cycle with an initiator abort.

PCI cycle frame.

is driven by the initiator of a bus cycle.

FRAME

FRAME

V07

is asserted to indicate that a bus transaction is beginning, and data

I/O

PCII3

PCIO3

VCCP

Pullup resistor per

FRAME

transfers continue while this signal is asserted. When FRAME is

PCI specification

deasserted, the PCI bus transaction is in the final data phase.

PCI bus grant.

is driven by the PCI bus arbiter to grant the

GNT

T02

controller access to the PCI bus after the current data transaction has

I

PCII3

VCCP

GNT

completed. GNT may or may not follow a PCI bus request, depending on

the PCI bus parking algorithm.

Initialization device select. IDSEL selects the controller during

IDSEL

W05

configuration space accesses. IDSEL can be connected to one of the

I

PCII3

VCCP

upper 24 PCI address lines on the PCI bus.

PCI initiator ready.

indicates the ability of the PCI bus initiator to

IRDY

complete the current data phase of the transaction. A data phase is

Pullup resistor per

U07

completed on a rising edge of PCLK where both IRDY and TRDY are

I/O

PCII3

PCIO3

VCCP

IRDY

PCI specification

asserted. Until IRDY and TRDY are both sampled asserted, wait states

are inserted.

PCI parity error indicator.

is driven by a PCI controller to indicate

PERR

Pullup resistor per

PERR

V08

that calculated parity does not match PAR when PERR is enabled

I/O

PCII3

PCIO3

VCCP

PCI specification

through bit 6 of the command register (PCI offset 04h, see Section 4.4).

PCI bus request.

is asserted by the controller to request access to

U01

REQ

O

PCIO3

VCCP

REQ

the PCI bus as an initiator.

PCI system error.

is an output that is pulsed from the controller

SERR

when enabled through bit 8 of the command register (PCI offset 04h,

U08

see Section 4.4) indicating a system error has occurred. The controller

O

PCIO3

VCCP

Pullup resistor per

SERR

PCI specification

need not be the target of the PCI cycle to assert this signal. When SERR

is enabled in the command register, this signal also pulses, indicating

that an address parity error has occurred on a CardBus interface.

PCI cycle stop signal.

is driven by a PCI target to request the

STOP

W08

initiator to stop the current PCI bus transaction. STOP is used for target

I/O

PCII3

PCIO3

VCCP

Pullup resistor per

STOP

disconnects and is commonly asserted by target devices that do not

PCI specification

support burst data transfers.

PCI target ready.

indicates the ability of the primary bus target to

TRDY

complete the current data phase of the transaction. A data phase is

Pullup resistor per

R08

completed on a rising edge of PCLK when both IRDY and TRDY are

I/O

PCII3

PCIO3

VCCP

TRDY

PCI specification

asserted. Until both IRDY and TRDY are asserted, wait states are

inserted.

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