Texas Instruments PCI7611 7. PCI Interrupt Pin Register, 8. Minimum Grant Register Description

13.14 Interrupt Pin Register

This register decodes the interrupt select inputs and returns the proper interrupt value based on Table 13−7, indicating that the Smart Card interface uses an interrupt. If one of the USE_INTx terminals is asserted, the interrupt select bits are ignored, and this register returns the interrupt value for the highest priority USE_INTx terminal that is asserted. If bit 28, the tie-all bit (TIEALL), in the system control register (PCI offset 80h, see Section 4.29) is set to 1, then the PCI7x21/PCI7x11 controller asserts the USE_INTA input to the Smart Card controller core. If bit 28 (TIEALL) in the system control register (PCI offset 80h, see Section 4.29) is set to 0, then none of the USE_INTx inputs are asserted and the interrupt for the Smart Card function is selected by the INT_SEL bits in the Smart Card general control register.

Bit	7	6	5	4		3	2	1	0
Name					Interrupt pin
Type	R	R	R	R		R	R	R	R
Default	0	0	0	0		0	X	X	X

Register: Interrupt pin

Offset: 3Dh

Type: Read-only

Default: 0Xh

Table 13−7. PCI Interrupt Pin Register

INT_SEL BITS	USE_INTA	INTPIN
00	0	01h
					(INTA)
01	0	02h
				(INTB)
10	0	03h
			(INTC)
11	0	04h
			(INTD)
XX	1	01h
					(INTA)

13.15 Minimum Grant Register

The minimum grant register contains the minimum grant value for the Smart Card controller core.

Bit		7	6	5		4	3	2	1		0
Name						Minimum grant
Type		RU	RU		RU	RU	RU	RU	RU		RU
Default		0	0	0		0	0	0	0		0
	Register:		Minimum grant
	Offset:		3Eh
	Type:		Read/Update
	Default:		00h
					Table 13−8. Minimum Grant Register Description
BIT	FIELD NAME		TYPE							DESCRIPTION
7−0	MIN_GNT		RU		Minimum grant. The contents of this field may be used by host BIOS to assign a latency timer register value
					to the Smart Card controller. The default for this register indicates that the Smart Card controller may need
					to sustain burst transfers for nearly 64 ∝s and thus request a large value be programmed in bits 15−8 of
					the PCI7x21/PCI7x11 latency timer and class cache line size register at offset 0Ch in the PCI configuration
					space (see Section 13.6).

13−9