Texas Instruments PCI7621, PCI7411, PCI7611, PCI7421 instruction

5.16 ExCA Memory Windows 0−4 End-Address High-Byte Registers

These registers contain the high nibble of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4. The lower 4 bits of these registers correspond to bits A23−A20 of the end address. In addition, the memory window wait states are set in this register. See Table 5−12 for a complete description of the register contents.

Bit

7

6

5

4

3

2

1

0

Name

ExCA memory windows 0−4 end-address high-byte

Type

RW

RW

R

R

RW

RW

RW

RW

Default

0

0

0

0

0

0

0

0

Register:

ExCA memory window 0 end-address high-byte

Offset:

CardBus Socket Address + 813h:

Card A ExCA Offset 13h

Card B ExCA Offset 53h

Register:

ExCA memory window 1 end-address high-byte

Offset:

CardBus Socket Address + 81Bh:

Card A ExCA Offset 1Bh

Card B ExCA Offset 5Bh

Register:

ExCA memory window 2 end-address high-byte

Offset:

CardBus Socket Address + 823h:

Card A ExCA Offset 23h

Card B ExCA Offset 63h

Register:

ExCA memory window 3 end-address high-byte

Offset:

CardBus Socket Address + 82Bh:

Card A ExCA Offset 2Bh

Card B ExCA Offset 6Bh

Register:

ExCA Memory window 4 end-address high-byte

Offset:

CardBus Socket Address + 833h:

Card A ExCA Offset 33h

Card B ExCA Offset 73h

Type:

Read/Write, Read-only

Default:

00h

Table 5−12. ExCA Memory Windows 0−4 End-Address High-Byte Registers Description

BIT

SIGNAL

TYPE

FUNCTION

7−6

MEMWS

RW

Wait state. These bits specify the number of equivalent ISA wait states to be added to 16-bit memory

accesses. The number of wait states added is equal to the binary value of these 2 bits.

5−4

RSVD

R

Reserved. These bits return 0s when read. Writes have no effect.

3−0

ENDHN

RW

End-address high nibble. These bits represent the upper address bits A23−A20 of the memory window end

address.

5−18

Image 146

Texas Instruments PCI7621, PCI7411, PCI7611, PCI7421 manual ExCA Memory Windows 0−4 End-Address High-Byte Registers

Contents

Data Manual Important Notice Contents −10 PC Card Controller Programming Model −1 ExCA Compatibility Registers Functions 0 and 1 −1 Vii Ohci Controller Programming Model −1Ohci Registers −1 Viii PHY Register Configuration 10−1TI Extension Registers −1 Flash Media Controller Programming Model −1 SD Host Controller Programming Model −1 Smart Card Controller Programming Model −1 Electrical Characteristics −1 Mechanical Information 15−1 List of Illustrations Xii List of Tables Xiii Functions 0 and 1 PCI Configuration Register Map Xiv Title −13 Xvi Xvii Xviii Controller Functional Description 1 PCI7621 Controller 2 PCI7421 Controller 3 PCI7611 Controller 4 PCI7411 Controller PCI Bus Power ManagementPower Switch Interface Multifunctional Terminals Features PCI Bus Interface Specification for PCI-to-CardBus Bridges PCI Local Bus Specification Revision Related Documents Trademarks −1. Terms and Definitions Terms and DefinitionsOrdering Information Term DefinitionsPage Terminal Descriptions −2. PCI7421 GHK/ZHK-Package Terminal Diagram −3. PCI7611 GHK/ZHK-Package Terminal Diagram −4. PCI7411 GHK/ZHK-Package Terminal Diagram −1. Signal Names by GHK Terminal Number Terminal Signal Name Number VCC BresetACC/BE2 VCC Acperr SCVCC5V ScclkBCC/BE0 BCE1 Latch RIOUT/PME Grst FrameGNT Perr Vsspll −2. CardBus PC Card Signal Names Sorted Alphabetically Signal Name Terminal Number Perr Trdy GND SdcmdPC2TEST3 Prst GND −3 -Bit PC Card Signal Names Sorted Alphabetically Signal Terminal Signal Name Number −12 Detailed Terminal Descriptions −13 −4. Power Supply Terminals −14 −15 −5. PC Card Power Switch Terminals−6. PCI System Terminals −7. PCI Address and Data Terminals −16 −8. PCI Interface Control Terminals −17 −9. Multifunction and Miscellaneous Terminals −18 −10 -Bit PC Card Address and Data Terminals −11 -Bit PC Card Interface Control Terminals Stschg AOE −12. CardBus PC Card Interface System Terminals PCIO3 Vccb −13. CardBus PC Card Address and Data Terminals BCAD0 −14. CardBus PC Card Interface Control Terminals BCCD2 Cstop −15. Ieee 1394 Physical Layer Terminals −26 −27 −16. SD/MMC Terminals−17. Memory Stick/PRO Terminals −18. Smart Media/XD Terminals −28 −19. Smart Card Terminals † −30 SD/MMC MS/MSPRO Power Supply SequencingEeprom SD/MMC Peripheral Component Interconnect PCI Interface I/O CharacteristicsClamping Voltages 1 1394 PCI Bus Master VCC Grst Prst Pclk Device ResetsSerial Eeprom I2C Bus Functions 0 and 1 CardBus Subsystem Identification ROM A1 SCL A2 SDA VCC Function 3 Flash Media Subsystem Identification PC Card ApplicationsFunction 2 Ohci 1394 Subsystem Identification Function 4 SD Host Subsystem Identification UltraMedia Card Detection PC Card Insertion/Removal and RecognitionLow Voltage CardBus Card Detection CD2//CCD2 CD1//CCD1 VS2//CVS2 VS1//CVS1 Flash Media Card Detection−2. PC Card-Card Detect and Voltage Sense Connections VCC VPP/VCORE −4. TPS2228 Control Logic-xVCC Internal Ring Oscillator−3. TPS2228 Control Logic-xVPP/VCORE −5. TPS2226 Control Logic-xVPP Spkrout and Caudpwm Usage LED Socket Activity IndicatorsIntegrated Pullup Resistors for PC Card Interface Spkrout Binaryspkr −7. CardBus Socket Registers CardBus Socket Registers11 48-MHz Clock Requirements LED Serial-Bus Interface Implementation Accessing Serial-Bus Devices Through SoftwareSerial Eeprom Interface Serial-Bus Interface Protocol −7. Serial-Bus Start/Stop Conditions and Bit Transfers −8. Serial-Bus Protocol Acknowledge Serial-Bus Eeprom Application −10. Serial-Bus Protocol-Byte Read GPE −9. Eeprom Loading MapSerial ROM Byte Description Offset PCI 2Dh, subsystem vendor ID, byte LinkEnh HCControl.Program Phy EnablePCI 2Ch, subsystem vendor ID, byte PCI 2Eh, subsystem ID, byte Programmable Interrupt Subsystem Card Type Event Mask Flag PC Card Functional and Card Status Change Interrupts−10. Interrupt Mask and Flag Registers −11. PC Card Interrupt Events and Description Card Type Event Signal DescriptionInterrupt Masks and Flags Using Parallel IRQ Interrupts Using Parallel PCI Interrupts SMI Support in the PCI7x21/PCI7x11 Controller Power Management OverviewUsing Serialized Irqser Interrupts −12. Interrupt Pin Register Cross Reference 1 1394 Power Management Function CardBus Functions 0 and 1 Clock Run Protocol CardBus PC Card Power ManagementIntegrated Low-Dropout Voltage Regulator LDO-VR Supply VCC Vren Vrport Requirements for Suspend Mode 5 16-Bit PC Card Power ManagementSuspend Mode Reset GNT Suspend Pclk Rienb Riout Ring IndicateCstsmask CSC Ringen RI Cdresume Power-management control/status CSR PCI Power Management−15. Power-Management Registers −17. Function 3 Power-Management Registers CardBus Bridge Power Management−16. Function 2 Power-Management Registers −18. Function 4 Power-Management Registers Master List of PME Context Bits and Global Reset-Only Bits Acpi Support −28 −29 Ieee 1394 Application Information PHY Port Cable Connection Crystal Selection −31 −32 Bus ResetCphy + CBD −33 −34 −2. Functions 0 and 1 PCI Configuration Register Map PCI Configuration Register Map Functions 0−1. Bit Field Access Tag Descriptions Access TAG Name Meaning Vendor ID Register Vendor ID Device ID Device ID-Smart Card enabledDevice ID Register Functions 0 −3. Command Register Description Command RegisterCommand BIT Signal Type Function −4. Status Register Description Status RegisterStatus Cache Line Size Register Revision ID RegisterClass Code Register Header Type Register Latency Timer RegisterRegister Latency timer Bist Register CardBus socket registers/ExCA base address CardBus Socket Registers/ExCA Base Address RegisterCapability Pointer Register Register Capability pointer −5. Secondary Status Register Description Secondary Status RegisterSecondary status Subordinate Bus Number Register PCI Bus Number RegisterCardBus Bus Number Register CardBus Memory Base Registers 0 CardBus Latency Timer RegisterRegister CardBus latency timer Memory base registers 0 Memory limit registers 0 CardBus Memory Limit Registers 0CardBus I/O Base Registers 0 Base registers 0 Limit registers 0 CardBus I/O Limit Registers 0Interrupt Line Register Register Interrupt line Interrupt Pin Register Interrupt pin − PCI function −6. Interrupt Pin Register Cross Reference Bridge Control RegisterInterrupt pin Bridge control Subsystem Vendor ID Register Subsystem vendor ID Subsystem ID Subsystem ID RegisterPC Card 16-Bit I/F Legacy-Mode Base-Address Register PC Card 16-bit I/F legacy-mode base-address −8. System Control Register Description System Control RegisterSystem control −8 . System Control Register Description Mccd Debounce Register Register Mccd debounce General control General Control RegisterGeneral control −9. General Control Register Description −10. General-Purpose Event Status Register Description General-Purpose Event Status RegisterGeneral-purpose event status General-Purpose Event Enable Register General-Purpose Input Register −13. General-Purpose Output Register Description General-Purpose Output RegisterGeneral-purpose output −14. Multifunction Routing Status Register Description Multifunction Routing Status RegisterMultifunction routing status −15. Retry Status Register Description Retry Status RegisterRetry status −16. Card Control Register Description Card Control RegisterCard control −17. Device Control Register Description Device Control RegisterDevice control −18. Diagnostic Register Description Diagnostic RegisterDiagnostic Register Capability ID Capability ID RegisterNext Item Pointer Register Register Next item pointer −19. Power Management Capabilities Register Description Power Management Capabilities RegisterPower management capabilities −20. Power Management Control/Status Register Description Power Management Control/Status RegisterPower management control/status Power-management data Power-Management Data RegisterPower management control/status bridge support extensions Bpccen Serial bus data Serial Bus Data RegisterSerial Bus Index Register −22. Serial Bus Data Register Description −24. Serial Bus Slave Address Register Description Serial Bus Slave Address RegisterRegister Serial bus slave address Rwcmd −25. Serial Bus Control/Status Register Description Serial Bus Control/Status RegisterSerial bus control/status −38 ExCA Compatibility Registers Functions 0 −1. ExCA Register Access Through I/O −1. ExCA Registers and Offsets Exca Register Name PCI Memory Address Exca Offset Offset HEX −2. ExCA Identification and Revision Register Description ExCA Identification and Revision RegisterExCA identification and revision Iftype −3. ExCA Interface Status Register Description ExCA Interface Status RegisterExCA interface status −4. ExCA Power Control Register Description-82365SL Support ExCA Power Control RegisterExCA power control −6. ExCA Interrupt and General Control Register Description ExCA Interrupt and General Control RegisterRegister ExCA interrupt and general control −7. ExCA Card Status-Change Register Description ExCA Card Status-Change RegisterExCA card status-change ExCA Card Status-Change Interrupt Configuration Register Register ExCA card status-change interrupt configuration −9. ExCA Address Window Enable Register Description ExCA Address Window Enable RegisterExCA address window enable −10. ExCA I/O Window Control Register Description ExCA I/O Window Control RegisterExCA I/O window control ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers ExCA I/O Windows 0 and 1 End-Address High-Byte Registers ExCA Memory Windows 0−4 Start-Address Low-Byte Registers ExCA Memory Windows 0−4 Start-Address High-Byte Registers ExCA Memory Windows 0−4 End-Address Low-Byte Registers ExCA Memory Windows 0−4 End-Address High-Byte Registers ExCA Memory Windows 0−4 Offset-Address Low-Byte Registers ExCA Memory Windows 0−4 Offset-Address High-Byte Registers ExCA Card Detect and General Control Register ExCA card detect and general control −15. ExCA Global Control Register Description ExCA Global Control RegisterExCA global control ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers ExCA Memory Windows 0−4 Page Registers Register ExCA memory windows 0−4 CardBus Socket Registers Functions 0 −2. Socket Event Register Description Socket Event RegisterSocket event −3. Socket Mask Register Description Socket Mask RegisterSocket mask −4. Socket Present State Register Description Socket Present State RegisterSocket present state Socket Force Event Register Socket force event −5. Socket Force Event Register Description −6. Socket Control Register Description Socket Control RegisterSocket control −7. Socket Power Management Register Description Socket Power Management RegisterSocket power management −1. Function 2 Configuration Register Map Pmcsrbse Device ID Register −2. Command Register Description BIT Field Name Type Description −3. Status Register Description Class Code and Revision ID Register Latency Timer and Class Cache Line Size RegisterLatency timer and class cache line size Class code and revision ID Header Type and Bist Register Ohci Base Address Register −8. TI Base Address Register Description TI Extension Base Address RegisterTI extension base address CardBus CIS base address CardBus CIS Base Address RegisterCardBus CIS Pointer Register −9. CardBus CIS Base Address Register Description Subsystem Identification Register Power Management Capabilities Pointer RegisterPower management capabilities pointer Subsystem identification BIT Field Name Type Description Intrline −11. Interrupt Line Register DescriptionRegister Interrupt pin 01h Inta 02h Intb 03h Intc Bits Intsel Minimum Grant and Maximum Latency Register Ohci Control Register Nextitem Capability ID and Next Item Pointer RegistersCapability ID and next item pointer Capabilityid −16. Power Management Capabilities Register Description Power management control and status Power Management Control and Status RegisterPower Management Extension Registers Power management extension −19. PCI PHY Control Register Description PCI PHY Control RegisterPCI PHY control Cnaout −20. PCI Miscellaneous Configuration Register Description PCI Miscellaneous Configuration RegisterPCI miscellaneous configuration −21. Link Enhancement Control Register Description Link Enhancement Control RegisterLink enhancement control −22. Subsystem Access Register Description Subsystem Access RegisterSubsystem access Subdevid −23. Gpio Control Register Description Gpio Control RegisterGpio control GPIODATA1 Disablebmc GPIO0GPIOENB1 GPIO1 = GPIO0 Guid ROM Guidrom −1. Ohci Register MapDMA Context Register Name Abbreviation Offset PhysicalRequestFilterHiClear IsoRecvIntEventClearIsochronous receive interrupt mask IsoRecvIntMaskSet Physical request filter low PhysicalRequestFilterLoSet ContextControlClear Isochronous receive context commandAsynchronous context control ContextControlSet Request Transmit Reserved −2. Ohci Version Register Description Ohci Version RegisterOhci version Guid ROM Guid ROM Register−3. Guid ROM Register Description RSU Asynchronous transmit retries Asynchronous Transmit Retries RegisterCSR Data Register −4. Asynchronous Transmit Retries Register Description CSR compare CSR Compare RegisterCSR Control Register CSR control −6. Configuration ROM Header Register Description Configuration ROM Header RegisterConfiguration ROM header Bus Identification Register −7. Bus Options Register Description Bus Options RegisterBus options Guid high Guid High RegisterGuid Low Register Guid low Configuration ROM Mapping Register Posted Write Address Low Register −10. Posted Write Address High Register Description Posted Write Address High RegisterPosted write address high −11. Host Controller Control Register Description Host Controller Control RegisterHost controller control RSU RSC Rscu LPS RSC Self-ID Buffer Pointer RegisterSelf-ID buffer pointer −12. Self-ID Count Register Description Self-ID Count RegisterSelf-ID count Isochronous Receive Channel Mask High Register Isochronous receive channel mask high Isochronous Receive Channel Mask Low Register Isochronous receive channel mask low −15. Interrupt Event Register Description Interrupt Event RegisterInterrupt event RSC Rscu Arrs Rscu Arrq Rscu Interrupt mask MasterIntEnableInterrupt Mask Register −16. Interrupt Mask Register Description Generation Arrs RSCArrq RSC Isochronous Transmit Interrupt Event Register Isochronous transmit interrupt event Isochronous Transmit Interrupt Mask Register Isochronous transmit interrupt mask Isochronous receive interrupt event Reserved. Bits 31−4 return 0s when readIsochronous Receive Interrupt Event Register Isochronous receive interrupt mask Isochronous Receive Interrupt Mask RegisterInitial Bandwidth Available Register Initial bandwidth available Initial Channels Available High Register Initial Channels Available Low Register −22. Fairness Control Register Description Fairness Control RegisterFairness control Value for this field is 00h −23. Link Control Register Description Link Control RegisterLink control −24. Node Identification Register Description Node Identification RegisterNode identification −25. PHY Control Register Description PHY Layer Control RegisterPHY layer control −26. Isochronous Cycle Timer Register Description Isochronous Cycle Timer RegisterIsochronous cycle timer −27. Asynchronous Request Filter High Register Description Asynchronous Request Filter High RegisterAsynchronous request filter high From that node are accepted −28. Asynchronous Request Filter Low Register Description Asynchronous Request Filter Low RegisterAsynchronous request filter low −29. Physical Request Filter High Register Description Physical Request Filter High RegisterPhysical request filter high PhysReqAllBusses That node are handled through the physical request context Physical request filter low Physical Request Filter Low RegisterPhysical Upper Bound Register Optional Register −30. Physical Request Filter Low Register Description −31. Asynchronous Context Control Register Description Asynchronous Context Control RegisterAsynchronous context control Rscu RSU DescriptorAddress Asynchronous Context Command Pointer RegisterAsynchronous context command pointer RSC RSU Isochronous Transmit Context Control RegisterIsochronous transmit context control Isochronous Receive Context Control Register Isochronous Transmit Context Command Pointer RegisterIsochronous transmit context command pointer Isochronous receive context control MultiChanMode When software clears bit 15 runNot be changed while bit 10 active or bit 15 run is set to Context match register see .46 is ignored Isochronous receive context command pointer Isochronous Receive Context Command Pointer RegisterIsochronous receive context command pointer −43 −35. Isochronous Receive Context Match Register Description Isochronous Receive Context Match RegisterIsochronous receive context match Link Enhancement Control Set DV and MPEG2 Timestamp Enhancements−1. TI Extension Register Map Link Enhancement Control Clear A8Ch Isochronous receive digital video enhancements Isochronous Receive Digital Video EnhancementsIsochronous Receive Digital Video Enhancements Register CIPStrip1 Reserved. Bits 7 and 6 return 0s when read420h/424h see .44 is cleared to Ohci offset 420h/424h see .44 is cleared to Link enhancement Reserved. Bit 11 returns 0 when read 10 ‡Link Enhancement Register −3. Link Enhancement Register Description −4. Timestamp Offset Register Description Timestamp Offset RegisterTimestamp offset Page Address BIT Position −1. Base Register ConfigurationBase Registers RHB IBR RHB −2. Base Register Field DescriptionsField Size Type Description Timeout Long bus reset being performedLLC to service the interrupt Is unaffected by bus reset −4. Page 0 Port Status Register Field Descriptions −3. Page 0 Port Status Register ConfigurationPort Status Register BIT Position Address Vendor Identification Register −5. Page 1 Vendor ID Register ConfigurationHardware reset and is unaffected by bus reset −6. Page 1 Vendor ID Register Field Descriptions −8. Page 7 Vendor-Dependent Register Field Descriptions −7. Page 7 Vendor-Dependent Register ConfigurationVendor-Dependent Register NPA Node does not need power and does not repeat power Power-Class Programming−9. Power Class Descriptions PC0-PC2 Description 10−8 −1. Function 3 Configuration Register Map Flash Media Controller Programming Model 11−2 Stepenb Pcispeed Devsel Is deasserted Programming interface. This field returns 00h when readStorage controller −7. Flash Media Base Address Register Description Flash Media Base Address RegisterFlash media base address Subsystem vendor identification Subsystem Vendor Identification RegisterCapabilities Pointer Register Capabilities pointer 11−8 −8. PCI Interrupt Pin RegisterIntsel Bits Useinta Intpin Minimum Grant Register Maximum Latency Register This field returns 00h when read −12. Power Management Capabilities Register Description Pmeen Power Management Bridge Support Extension RegisterPmestat RCU PME Rsvd −14. General Control Register Power Management Data RegisterPower management data Register at PCI offset 2Ch 11−14 −15. Subsystem Access Register DescriptionSubsystemVendorID Tbdctrl −16. Diagnostic Register DescriptionDiagnostic Plln 11−16 Maximum current −1. Function 4 Configuration Register MapSlot information 12−2 Transactions therefore, bit 4 returns 0 when read Therefore, bit 9 returns 0 when readBit 5 returns 0 when read Bit 3 returns 0 when read Syserr RCU 12−5 PeripheralDMA capabilities 12−6 Memory-read line, and memory-read multiple transactionsRead −7. SD host Base Address Register Description SD Host Base Address RegisterSD host base address Type 12.12 Interrupt Line Register 12−8 Space see Section 12−9 −11. Maximum Latency Register Description Slot Information RegisterRegister Maximum latency Numberslots 12−11 Controller to generate PME −13. Power Management Capabilities Register DescriptionDriver is able to use it Revision 12−12 Register Power management bridge support extensionEnable. Enables Signaling 12−13 Dmaen −15. General Control Register01 = Intb 10 = Intc 11 = Intd Dmasupport bit of each SD host socket is Reserved. Bits 31−17 return 0s when read −16. Subsystem Access Register Description−17. Diagnostic Register Description Register at PCI offset 2Ch Slot 2 3.3-V Maximum Current Register Slot 0 3.3-V Maximum Current RegisterSlot 1 3.3-V Maximum Current Register Slot 5 3.3-V Maximum Current Register Slot 3 3.3-V Maximum Current RegisterSlot 4 3.3-V Maximum Current Register 12−18 60h−FCh −1. Function 5 Configuration Register Map1Ch−28h 13−2 Intdis Seren Intstat Is enabled and the Smart Card controller hasTabtsig RCU 13−4 Offset 08h Type Read-only Default 0780 0000h Card is a multifunction device Smart Card Base Address RegisterSmart Card base address register Smart Card base address register 13−7 Smart Card Base Address Register 1−4Smart Card base address register 1−4 13.13 Interrupt Line Register 13−8 Space see Section 13−9 −7. PCI Interrupt Pin Register−8. Minimum Grant Register Description −9. Maximum Latency Register Description 13−10 PMED2 −11. Power Management Capabilities Register DescriptionPMED3HOT PMED1 PMED0 D2SUPPORT 13−12 PME Grst RsvdDstate Pin = 01 = Intb pin = 10 = Intc pin = 11 = Intd pin = Gated to reduce power consumption−13. General Control Register Subsystem ID alias Subsystem ID Alias RegisterClass Code Alias Register −14. Subsystem ID Alias Register Description Smart Card configuration Smart Card Configuration 1 RegisterSmart Card configuration 13−15 −15. Smart Card Configuration 1 Register Description Pwrupdelay Smart Card Configuration 2 Register−16. Smart Card Configuration 2 Register Description Reserved. Bits 7−0 return 0s when read 13−17 13−18 Operation MIN NOM MAX Unit Absolute Maximum Ratings Over Operating Temperature Ranges†Recommended Operating Conditions see Note Avdd VCC VDPLL15 VDPLL33 Vccp Recommended Operating Conditions TJ# Parameter Terminals Operation Test Conditions MIN MAX Unit 14.4.3 Receiver 14.4.1 Device14.4.2 Driver Parameter Test Condition MIN MAX Unit Parameter Alternate Test Conditions MIN MAX Unit Switching Characteristics for PHY Port InterfaceOperating, Timing, and Switching Characteristics Parameter Test Conditions MIN TYP MAX Unit Mechanical Information 15−2 Package Option Addendum