Table 8−1. OHCI Register Map (Continued)

DMA CONTEXT

REGISTER NAME

ABBREVIATION

OFFSET

 

 

 

 

Self-ID

Reserved

60h

 

 

 

 

 

Self-ID buffer pointer

SelfIDBuffer

64h

 

 

 

 

 

Self-ID count

SelfIDCount

68h

 

 

 

 

 

Reserved

6Ch

 

 

 

 

Isochronous receive channel mask high

IRChannelMaskHiSet

70h

 

 

 

 

IRChannelMaskHiClear

74h

 

 

 

 

 

 

 

Isochronous receive channel mask low

IRChannelMaskLoSet

78h

 

 

 

 

IRChannelMaskLoClear

7Ch

 

 

 

 

 

 

 

Interrupt event

IntEventSet

80h

 

 

 

 

IntEventClear

84h

 

 

 

 

 

 

 

Interrupt mask

IntMaskSet

88h

 

 

 

 

IntMaskClear

8Ch

 

 

 

 

 

 

 

Isochronous transmit interrupt event

IsoXmitIntEventSet

90h

 

 

 

 

IsoXmitIntEventClear

94h

 

 

 

 

 

 

 

Isochronous transmit interrupt mask

IsoXmitIntMaskSet

98h

 

 

 

 

IsoXmitIntMaskClear

9Ch

 

 

 

 

 

 

Isochronous receive interrupt event

IsoRecvIntEventSet

A0h

 

 

 

 

IsoRecvIntEventClear

A4h

 

 

 

 

 

 

 

Isochronous receive interrupt mask

IsoRecvIntMaskSet

A8h

 

 

 

 

IsoRecvIntMaskClear

ACh

 

 

 

 

 

 

 

Initial bandwidth available

InitialBandwidthAvailable

B0h

 

 

 

 

 

Initial channels available high

InitialChannelsAvailableHi

B4h

 

 

 

 

 

Initial channels available low

InitialChannelsAvailableLo

B8h

 

 

 

 

 

Reserved

BCh−D8h

 

 

 

 

 

Fairness control

FairnessControl

DCh

 

 

 

 

 

Link control ‡

LinkControlSet

E0h

 

 

 

 

LinkControlClear

E4h

 

 

 

 

 

 

 

Node identification

NodeID

E8h

 

 

 

 

 

PHY layer control

PhyControl

ECh

 

 

 

 

 

Isochronous cycle timer

Isocyctimer

F0h

 

 

 

 

 

Reserved

F4h−FCh

 

 

 

 

 

Asynchronous request filter high

AsyncRequestFilterHiSet

100h

 

 

 

 

AsyncRequestFilterHiClear

104h

 

 

 

 

 

 

 

Asynchronous request filter low

AsyncRequestFilterLoSet

108h

 

 

 

 

AsyncRequestFilterLoClear

10Ch

 

 

 

 

 

 

 

Physical request filter high

PhysicalRequestFilterHiSet

110h

 

 

 

 

PhysicalRequestFilterHiClear

114h

 

 

 

 

 

 

 

Physical request filter low

PhysicalRequestFilterLoSet

118h

 

 

 

 

PhysicalRequestFilterLoClear

11Ch

 

 

 

 

 

 

 

Physical upper bound

PhysicalUpperBound

120h

 

 

 

 

 

Reserved

124h−17Ch

 

 

 

 

One or more bits in this register are cleared only by the assertion of GRST.

8−2

Page 182
Image 182
Texas Instruments PCI7621, PCI7411, PCI7611 manual IsoRecvIntEventClear, Isochronous receive interrupt mask IsoRecvIntMaskSet