Texas Instruments PCI7621, PCI7411, PCI7611, PCI7421 manual 7. PCI Address and Data Terminals, 16

Table 2−7. PCI Address and Data Terminals

Internal pullup/pulldown resistors and pin strapping are not applicable for the PCI address and data terminals.

TERMINAL		DESCRIPTION	I/O	INPUT	OUTPUT	POWER
NAME	NO.		TYPE			RAIL
AD31	U02
AD30	V01
AD29	V02
AD28	U03
AD27	W02
AD26	V03
AD25	U04
AD24	V04
AD23	V05
AD22	U05
AD21	R06
AD20	P06
AD19	W06
AD18	V06
AD17	U06
AD16	R07	PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the
		primary interface. During the address phase of a primary-bus PCI cycle, AD31−AD0 contain a	I/O	PCII3	PCIO3	VCCP
AD15	V09
		32-bit address or other destination information. During the data phase, AD31−AD0 contain data.
AD14	U09
AD13	R09
AD12	N09
AD11	V10
AD10	U10
AD9	R10
AD8	N10
AD7	V11
AD6	U11
AD5	R11
AD4	W12
AD3	V12
AD2	U12
AD1	N11
AD0	W13
	W04	PCI-bus commands and byte enables. These signals are multiplexed on the same PCI
C/BE3
		terminals. During the address phase of a primary-bus PCI cycle, C/BE3−C/BE0 define the bus
	W07
C/BE2		command. During the data phase, this 4-bit bus is used as byte enables. The byte enables	I/O	PCII3	PCIO3	VCCP
	W09	determine which byte paths of the full 32-bit data bus carry meaningful data. C/BE0 applies to
C/BE1
	W11	byte 0 (AD7−AD0), C/BE1 applies to byte 1 (AD15−AD8), C/BE2 applies to byte 2
C/BE0
		(AD23−AD16), and C/BE3 applies to byte 3 (AD31−AD24).
		PCI-bus parity. In all PCI-bus read and write cycles, the controller calculates even parity across
		the AD31−AD0 and C/BE3 −C/BE0 buses. As an initiator during PCI cycles, the controller
PAR	P09	outputs this parity indicator with a one-PCLK delay. As a target during PCI cycles, the controller	I/O	PCII3	PCIO3	VCCP
		compares its calculated parity to the parity indicator of the initiator. A compare error results in
		the assertion of a parity error (PERR).

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