Texas Instruments PCI7421, PCI7411, PCI7611, PCI7621 manual 4. Status Register Description

Table 4−3. Command Register Description (continued)

BIT	SIGNAL	TYPE		FUNCTION
			Memory space enable. This bit controls whether or not the PCI7x21/PCI7x11 controller can claim cycles
1	MEM_EN	RW	in PCI memory space.
			0	= Disables the PCI7x21/PCI7x11 response to memory space accesses (default)
			1	= Enables the PCI7x21/PCI7x11 response to memory space accesses
			I/O space control. This bit controls whether or not the PCI7x21/PCI7x11 controller can claim cycles in PCI
0	IO_EN	RW	I/O space.
			0	= Disables the PCI7x21/PCI7x11 controller from responding to I/O space accesses (default)
			1	= Enables the PCI7x21/PCI7x11 controller to respond to I/O space accesses

4.5 Status Register

The status register provides device information to the host system. Bits in this register can be read normally. A bit in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. All bit functions adhere to the definitions in the PCI Bus Specification, as seen in the bit descriptions. PCI bus status is shown through each function. See Table 4−4 for a complete description of the register contents.

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Status

Type

RW

RW

RW

RW

RW

R

R

RW

R

R

R

R

RU

R

R

R

Default

0

0

0

0

0

0

1

0

0

0

0

1

0

0

0

0

Register:

Status

Offset:

06h (Functions 0, 1)

Type:

Read-only, Read/Write

Default:

0210h

Table 4−4. Status Register Description

BIT

SIGNAL

TYPE

FUNCTION

15 ‡

PAR_ERR

RW

Detected parity error. This bit is set when a parity error is detected, either an address or data parity error.

Write a 1 to clear this bit.

14 ‡

SYS_ERR

RW

Signaled system error. This bit is set when

SERR

is enabled and the PCI7x21/PCI7x11 controller signaled

a system error to the host. Write a 1 to clear this bit.

13 ‡

MABORT

RW

Received master abort. This bit is set when a cycle initiated by the PCI7x21/PCI7x11 controller on the PCI

bus has been terminated by a master abort. Write a 1 to clear this bit.

12 ‡

TABT_REC

RW

Received target abort. This bit is set when a cycle initiated by the PCI7x21/PCI7x11 controller on the PCI

bus was terminated by a target abort. Write a 1 to clear this bit.

11 ‡

TABT_SIG

RW

Signaled target abort. This bit is set by the PCI7x21/PCI7x11 controller when it terminates a transaction on

the PCI bus with a target abort. Write a 1 to clear this bit.

10−9

PCI_SPEED

R

DEVSEL timing. These bits encode the timing of

DEVSEL

and are hardwired to 01b indicating that the

PCI7x21/PCI7x11 controller asserts this signal at a medium speed on nonconfiguration cycle accesses.

Data parity error detected. Write a 1 to clear this bit.

0 = The conditions for setting this bit have not been met.

8 ‡

DATAPAR

RW

1 = A data parity error occurred and the following conditions were met:

a. PERR was asserted by any PCI device including the PCI7x21/PCI7x11 controller.

b. The PCI7x21/PCI7x11 controller was the bus master during the data parity error.

c. The parity error response bit is set in the command register.

7

FBB_CAP

R

Fast back-to-back capable. The PCI7x21/PCI7x11 controller cannot accept fast back-to-back transactions;

thus, this bit is hardwired to 0.

6

UDF

R

UDF supported. The PCI7x21/PCI7x11 controller does not support user-definable features; therefore, this

bit is hardwired to 0.

5

66MHZ

R

66-MHz capable. The PCI7x21/PCI7x11 controller operates at a maximum PCLK frequency of 33 MHz;

therefore, this bit is hardwired to 0.

‡ This bit is cleared only by the assertion of GRST.

4−5