Intel 8XC196MD Table B-5. Description of Columns of Table B-6, Table B-6. Signal Descriptions

				SIGNAL DESCRIPTIONS
		Table B-5. Description of Columns of Table B-6
Column Heading				Description
Name				Lists the signals, arranged alphabetically. Many pins have two functions, so
				there are more entries in this column than there are pins. Every signal is
				listed in this column.
Type				Identifies the pin function listed in the Name column as an input (I), output
				(O), bidirectional (I/O), power (PWR), or ground (GND).
				Note that all inputs except RESET# are sampled inputs. RESET# is a level-
				sensitive input. During powerdown mode, the powerdown circuitry uses
				EXTINT as a level-sensitive input.
Description				Briefly describes the function of the pin for the specific signal listed in the
				Name column. Also lists any alternate fuctions that are multiplexed with the
				signal.
				Table B-6. Signal Descriptions
Name	Type			Description
ACH12:0 (MC)	I		Analog Channels
ACH13:0 (MD)			These pins are analog inputs to the A/D converter.
ACH7:0 (MH)			These pins may individually be used as analog inputs (ACHx) or digital inputs
			(P0.y). While it is possible for the pins to function simultaneously as analog and
			digital inputs, this is not recommended because reading port 0 while a
			conversion is in process can produce unreliable conversion results.
			The ANGND and VREF pins must be connected for the A/D converter and port 0
			to function.
			ACH7:0 are multiplexed as follows: ACH0/P0.0, ACH1/P0.1, ACH2/P0.2,
			ACH3/P0.3, ACH4/P0.4/PMODE.0, ACH5/P0.5/PMODE.1,
			ACH6/P0.6/PMODE.2, ACH7/P0.7/PMODE.3, ACH8/P1.0, ACH9/P1.1,
			ACH10/P1.2/T1CLK, ACH11/P1.3/T1DIR, and ACH12/P1.4, and ACH13/P1.5.
			ACH13 is not implemented on the 8XC196MC and ACH13:8 are not
			implemented on the 8XC196MH.
AD15:0	I/O		Address/Data Lines
			These pins provide a multiplexed address and data bus. During the address
			phase of the bus cycle, address bits 0–15 are presented on the bus and can be
			latched using ALE or ADV#. During the data phase, 8- or 16-bit data is trans-
			ferred.
			AD7:0 are multiplexed with P3.7:0, and PBUS.7:0. AD15:8 are multiplexed with
			P4.7:0 and PBUS.15:8.
ADV#	O		Address Valid
			This active-low output signal is asserted only during external memory
			accesses. ADV# indicates that valid address information is available on the
			system address/data bus. The signal remains low while a valid bus cycle is in
			progress and is returned high as soon as the bus cycle completes.
			An external latch can use this signal to demultiplex the address from the
			address/data bus. A decoder can also use this signal to generate chip selects
			for external memory.
			ADV# is multiplexed with P5.0 and ALE.

B-13