Intel 8XC196MD, 8XC196MH Autoinc Short Long Reg, LDB Ldbse Ldbze STB XCH Xchb, Ljmp Sjmp Tijmp

INSTRUCTION SET REFERENCE

Table A-9. Instruction Execution Times (in State Times) (Continued)

				Data
Mnemonic	Indirect
BMOV	register/register		6 + 8 per word
	memory/register		6 + 11 per word
	memory/memory		6 + 14 per word
BMOVI	register/register		7 + 8 per word + 14 per interrupt
	memory/register		7 + 11 per word + 14 per interrupt
	memory/memory		7 + 14 per word + 14 per interrupt
					Indirect								Indexed
Mnemonic	Direct	Immed.	Normal					Autoinc.			Short				Long
			Reg.		Mem.		Reg.		Mem.		Reg.	Mem.		Reg.		Mem.
LD	4	5	5		8			6		8	6		9	7		10
LDB	4	4	5		8			6		8	6		9	7		10
LDBSE	4	4	5		8			6		8	6		9	7		10
LDBZE	4	4	5		8			6		8	6		9	7		10
ST	4	—	5		8			6		9	6		9	7		10
STB	4	—	5		8			6		8	6		9	7		10
XCH	5	—	—		—	—		—		8	13		9		14
XCHB	5	—	—		—	—		—		8	13		9		14
				Jump
Mnemonic	Direct	Immed.			Indirect								Indexed
			Normal					Autoinc.			Short				Long
BR	—	—		7				7			—			—
LJMP	—	—		—				—			—			7
SJMP	—	—		—				—			7			—
TIJMP
register/register	—	—		15				—			—				—
memory/register				18
memory/memory				21
			Call (Register)
Mnemonic	Direct	Immed.			Indirect								Indexed
			Normal					Autoinc.			Short				Long
LCALL	—	—		—				—			—			11
RET	—	—		11				—			—			—
SCALL	—	—		—				—			—			11
TRAP	16	—		—				—			—			—

NOTE: The column entitled “Reg.” lists the instruction execution times for accesses to the register file or peripheral SFRs. The column entitled “Mem.” lists the instruction execution times for accesses to all memory-mapped registers, I/O, or memory. See Table 4-1 on page 4-2 for address information.

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