EPA Control and Status Registers | Intel 8XC196MC, 8XC196MD specification

						EVENT PROCESSOR ARRAY (EPA)
	Table 11-2. EPA and Timer/Counter Signals (Continued)

	Port Pin				EPA	EPA
					EPA	Signal	Description
8XC196MC	8XC196MD		8XC196MH		Signals	Signal	Description
					Signals	Type
						Type

P2.4	P2.4			P2.4	COMP0	O	Output of the compare-only channels.
P2.5	P2.5			P2.5	COMP1
P2.6	P2.6			P2.6	COMP2
P2.7	P2.7			P2.3	COMP3
—	P7.2			—	COMP4
—	P7.3			—	COMP5
		Table 11-3. EPA Control and Status Registers

Mnemonic				Address			Description

		MC		MD	MH
		MC		MD	MH

COMP0_CON		1F58H		1F58H	1F58H	EPAx Compare Control
COMP1_CON		1F5CH		1F5CH	1F5CH	These registers control the functions of the
COMP2_CON		1F60H		1F60H	1F60H	These registers control the functions of the
COMP2_CON		1F60H		1F60H	1F60H	compare-only channels.
COMP3_CON		1F64H		1F64H	1F4CH	compare-only channels.
COMP3_CON		1F64H		1F64H	1F4CH
COMP4_CON		—		1F68H	—
COMP5_CON		—		1F6CH	—
COMP0_TIME		1F5AH		1F5AH	1F5AH	EPAx Compare Time
COMP1_TIME		1F5EH		1F5EH	1F5EH	These registers contain the time at which an event
COMP2_TIME		1F62H		1F62H	1F62H	These registers contain the time at which an event
COMP2_TIME		1F62H		1F62H	1F62H	is to occur on the compare-only channels.
COMP3_TIME		1F66H		1F66H	1F4EH	is to occur on the compare-only channels.
COMP3_TIME		1F66H		1F66H	1F4EH
COMP4_TIME		—		1F6AH	—
COMP5_TIME		—		1F6EH	—
EPA0_CON		1F40H		1F40H	1F40H	EPAx Capture/Compare Control
EPA1_CON		1F44H		1F44H	1F44H	These registers control the functions of the
EPA2_CON		1F48H		1F48H	—	These registers control the functions of the
EPA2_CON		1F48H		1F48H	—	capture/compare channels. EPA1_CON and
EPA3_CON		1F4CH		1F4CH	—	capture/compare channels. EPA1_CON and
EPA3_CON		1F4CH		1F4CH	—	EPA3_CON require an extra byte because they
EPA4_CON		—		1F50H	—	EPA3_CON require an extra byte because they
EPA4_CON		—		1F50H	—	contain an	additional bit for PWM remap mode.
EPA5_CON		—		1F54H	—	contain an	additional bit for PWM remap mode.
EPA5_CON		—		1F54H	—	These two registers must be addressed as words;
						These two registers must be addressed as words;
						the others can be addressed as bytes.
EPA0_TIME		1F42H		1F42H	1F42H	EPAx Capture/Compare Time
EPA1_TIME		1F46H		1F46H	1F46H	In capture mode, these registers contain the
EPA2_TIME		1F4AH		1F4AH	—	In capture mode, these registers contain the
EPA2_TIME		1F4AH		1F4AH	—	captured timer value. In compare mode, these
EPA3_TIME		1F4EH		1F4EH	—	captured timer value. In compare mode, these
EPA3_TIME		1F4EH		1F4EH	—	registers contain the time at which an event is to
EPA4_TIME		—		1F52H	—	registers contain the time at which an event is to
EPA4_TIME		—		1F52H	—	occur. In capture mode, these registers are
EPA5_TIME		—		1F56H	—	occur. In capture mode, these registers are
EPA5_TIME		—		1F56H	—	buffered to allow two captures before an overrun
						buffered to allow two captures before an overrun
						occurs. However, they are not buffered in compare
						mode.
INT_MASK		0008H		0008H	0008H	Interrupt Mask
						The bits in this 8-bit register enable and disable
						(mask) the interrupts associated with the corre-
						sponding bits in the INT_PEND register.
INT_MASK1		0013H		0013H	0013H	Interrupt Mask 1
						The bits in this 8-bit register enable and disable
						(mask) the interrupts associated with the corre-
						sponding bits in the INT_PEND1 register.

11-3

Intel 8XC196MC, 8XC196MD, 8XC196MH manual EPA Control and Status Registers

Models: 8XC196MD 8XC196MH 8XC196MC

Table 11-2. EPA and Timer/Counter Signals (Continued)

EPA

Description

Table 11-3. EPA Control and Status Registers

Mnemonic

Address

Description

EPA5_TIME

INT_MASK1