Intel 8XC196MC, 8XC196MD, 8XC196MH manual SCLK10# Shift Clock 0 MH only

SIGNAL DESCRIPTIONS

		Table B-6. Signal Descriptions (Continued)
Name	Type	Description
SCLK1:0#	I/O	Shift Clock 0 and 1
(MH only)		In SIO mode 4, SCLKx# are bidirectional shift clock signals that synchronize the
		serial data transfer. The DIR bit in the SP_CON register controls the direction of
		SCLKx#.
		DIR = 1 allows an external shift clock to be input on SCLKx#.
		DIR = 0 causes SCLKx# to output the internal shift clock.
		SCLK0# is multiplexed with P2.1, BCLK0, and PALE#. SCLK1# is multiplexed
		with P2.7 and BCLK1.
T1CLK	I	Timer 1 External Clock
		External clock for timer 1. Timer 1 increments (or decrements) on both rising
		and falling edges of T1CLK. Also used in conjunction with T1DIR for
		quadrature counting mode.
		and
		External clock for the serial I/O baud-rate generator input (program selectable).
		On the 8XC196MC and MD, T1CLK is multiplexed with P1.2 and ACH10. On
		the 8XC196MH, T1CLK is multiplexed with P0.6, ACH6, and PMODE.2.
T1DIR	I	Timer 1 External Direction
		External direction (up/down) for timer 1. Timer 1 increments when T1DIR is high
		and decrements when it is low. Also used in conjunction with T1CLK for
		quadrature counting mode.
		On the 8XC196MC and MD, T1DIR is multiplexed with P1.3 and ACH11. On the
		8XC196MH, T1DIR is multiplexed with P0.7, ACH7, and PMODE.3.
TXD1:0	O	Transmit Serial Data 0 and 1
(MH only)		In serial I/O modes 1, 2, and 3, TXD0 and 1 transmit serial port output data. In
		mode 0, they are the serial clock outputs.
		TXD0 is multiplexed with P1.0 and TXD1 is multiplexed with P1.2.
		TXD0 and 1 are not implemented on the 8XC196MC and MD.
VCC	PWR	Digital Supply Voltage
		Connect each VCC pin to the digital supply voltage.
VPP	PWR	Programming Voltage
		During programming, the VPP pin is typically at +12.5 V (VPP voltage).
		Exceeding the maximum VPP voltage specification can damage the device.
		VPP also causes the device to exit powerdown mode when it is driven low for at
		least 50 ns. Use this method to exit powerdown only when using an external
		clock source because it enables the internal phase clocks, but not the internal
		oscillator. See “Driving the Vpp Pin Low” on page 14-6.
		On devices with no internal nonvolatile memory, connect VPP to VCC.
VREF	PWR	Reference Voltage for the A/D Converter
		This pin also supplies operating voltage to both the analog portion of the A/D
		converter and the logic used to read port 0 (also port 1 in the 8XC196MC and
		8XC196MD).
VSS	GND	Digital Circuit Ground
		These pins supply ground for the digital circuitry. Connect each VSS pin to
		ground through the lowest possible impedance path.

B-21