Intel 8XC196MD, 8XC196MH, 8XC196MC manual Phase Driver Channels, Control and Protection Circuitry

WAVEFORM GENERATOR

9.3.2Phase Driver Channels

The phase driver channels determine the duty cycle of the outputs. You specify the duty cycle by writing a value to each phase’s compare register (WG_COMP x). In all operating modes, the out- puts are initially asserted, and they remain asserted until the counter value (WG_COUNTER) matches the phase’s compare register (WG_COMP x) value. At this point, the outputs are deas- serted and remain deasserted until another event occurs. The event that causes the outputs to be asserted again depends on the operating mode. (See “Operating Modes” on page 9-7.)

The dead-time generator circuitry (Figure 9-2) prevents an output and its complement from being asserted at the same time. It uses two internal signals, WFG and DT, to generate the nonoverlap- ping outputs. The edge-detection circuitry generates the WFG signal, while a 10-bit dead-time counter generates the DT signal. When a valid edge is detected, the dead-time counter is loaded with the 10-bit dead-time value from the control register and DT is driven low. The counter dec- rements once every state time until it reaches zero, at which point the counter stops and DT is driven high. The WFG signal is ANDed with DT to produce the WG_EVEN signal; the WFG# signal is ANDed with DT to produce the WG_ODD signal. The waveform generator’s outputs can be connected to the WG_EVEN and WG_ODD signals. (See “Configuring the Outputs” on page 9-12.)

							Output Disable
								From
			10-Bit Value				Protection Circuit
	WG_CONTROL				To Other
		Bits 0 – 9			Channels
								WG_EVEN
		Transition
From		Detector							P6.0 / WG1#
Phase		Trigger	10-Bit Counter	DT				Output
			Start/ CNT=0
Comparator								Circuitry
		Both	Load						P6.1 / WG1
		Edges						WG_ODD
			WFG
						WFG#
									A2640-01

Figure 9-2. Dead-time Generator Circuitry

9.3.3Control and Protection Circuitry

The control circuitry contains the control (WG_CONTROL) and output (WG_OUTPUT) regis- ters. The control register enables or disables the counter, specifies the count direction, controls the operating mode, and specifies the dead time for all three phases. The output register config- ures the pins, specifies the output polarity (active high or active low), and controls whether the outputs are updated immediately or are synchronized with an event.

9-5