Range of 0 to 31 1FH, inclusive. If | Intel 8XC196MD, 8XC196MH

8XC196MC, MD, MH USER’S MANUAL

Table A-6. Instruction Set (Continued)

Mnemonic

Operation

Instruction Format

SHRA

ARITHMETIC RIGHT SHIFT WORD. Shifts

the destination word operand to the right as

SHRA

wreg, #count

many times as specified by the count

(00001010) (count) (wreg)

operand. The count may be specified either

as an immediate value in the range of 0 to 15

or

(0FH), inclusive, or as the content of any

SHRA

wreg, breg

register (10H – 0FFH) with a value in the

(00001010) (breg) (wreg)

range of 0 to 31 (1FH), inclusive. If the

original high order bit value was “0,” zeros are

shifted in. If the value was “1,” ones are

NOTES:

This instruction clears the

shifted in. The last bit shifted out is saved in

sticky bit flag at the beginning

the carry flag.

of the instruction. If at any time

Temp ← (COUNT)

during the shift a “1” is shifted

do while Temp ≠ 0

into the carry flag and another

C ← Low order bit of (DEST)

shift cycle occurs, the instruc-

(DEST) ← (DEST)/2

tion sets the sticky bit flag.

Temp ← Temp – 1

end_while

In this operation, (DEST)/2 rep-

resents signed division.

PSW Flag Settings

Z

N

C

V

VT

ST

✓

✓

✓

0

—

✓

SHRAB

ARITHMETIC RIGHT SHIFT BYTE. Shifts the

destination byte operand to the right as many

SHRAB

breg, #count

times as specified by the count operand. The

(00011010) (count) (breg)

count may be specified either as an

or

immediate value in the range of 0 to 15

(0FH), inclusive, or as the content of any

SHRAB

breg, breg

register (10H – 0FFH) with a value in the

(00011010) (breg) (breg)

range of 0 to 31 (1FH), inclusive. If the

original high order bit value was “0,” zeros are

shifted in. If the value was “1,” ones are

NOTES:

This instruction clears the

shifted in. The last bit shifted out is saved in

sticky bit flag at the beginning

the carry flag.

of the instruction. If at any time

Temp ← (COUNT)

during the shift a “1” is shifted

do while Temp ≠ 0

into the carry flag and another

C = Low order bit of (DEST)

shift cycle occurs, the instruc-

(DEST) ← (DEST)/2

tion sets the sticky bit flag.

Temp ← Temp – 1

end_while

In this operation, (DEST)/2 rep-

resents signed division.

PSW Flag Settings

Z

N

C

V

VT

ST

✓

✓

✓

0

—

✓

A-34

Image 423

Intel 8XC196MD, 8XC196MH, 8XC196MC manual Range of 0 to 31 1FH, inclusive. If

Contents

8XC196MC, 8XC196MD, 8XC196MH Microcontroller User’ Manual We Value Your Opinion Page 8XC196MC, 8XC196MD, 8XC196MH Microcontroller User’s Manual Intel Corporation Contents Chapter Memory Partitions Contents 8XC196MC, MD, MH USER’S Manual Programming the Waveform Generator PWM Signals and RegistersFunctional Overview Programming the Frequency Generator Application Example Chapter Event Processor Array EPA Chapter Minimum Hardware Considerations Chapter Programming the Nonvolatile Memory Appendix C Registers Glossary Index Figures 10-5 15-9 Ready Timing Diagram One Wait State 8XC196MH 15-21 Tables 11-12 16-7 Pmode Values Guide to This Manual Page Chapter Guide to this Manual Manual Contents Special Operating Modes Assert and deassert Notational Conventions and Terminology Numbers Related Documents Handbooks and Product Information Application Notes, Application Briefs, and Article ReprintsTitle Order Number MCS 96 Microcontroller Datasheets Automotive MCS 96 Microcontroller Datasheets Commercial/Express This Page Left Intentionally Blank Guide to this Manual This Page Left Intentionally Blank World Wide Web Technical SupportProduct Literature Page Architectural Overview Page Typical Applications Microcontroller Features SIO PWM Features of the 8XC196Mx Product FamilyFunctional Overview Otprom RAM ROMPTS EPA PWM WDT SIO CPU CPU Control Register FileRegister Arithmetic-logic Unit Ralu Instruction Format Code Execution Memory Interface Unit Interrupt Service Clock Circuitry Internal Timing State Times at Various Frequencies Internal Peripherals Serial I/O SIO Port 1 I/O Ports Waveform Generator Event Processor Array EPA and Timer/CountersPulse-width Modulator PWM Frequency Generator Analog-to-digital Converter Watchdog TimerReducing Power Consumption Testing the Printed Circuit Board Programming the Nonvolatile Memory Programming Considerations Page Restrictions Overview of the Instruction SETOperand Type Definitions Operand Type No. Signed Possible Values Addressing Word Operands BIT OperandsByte Operands SHORT-INTEGER Operands DOUBLE-WORD Operands Integer Operands Floating Point Operations LONG-INTEGER OperandsConverting Operands Conditional Jumps Addressing Modes Definition of Temporary Registers Direct AddressingImmediate Addressing Indirect Addressing Short-indexed Addressing Indexed AddressingIndirect Addressing with Autoincrement Indirect Addressing with the Stack Pointer Zero-indexed Addressing Long-indexed Addressing Assembly Language Addressing Mode Selections Using RegistersSoftware Standards and Conventions Linking Subroutines Addressing 32-bit Operands Software Protection Features and Guidelines 8XC196MC, MD, MH USER’S Manual Memory Partitions Page Memory Partitions External Devices Memory or I/OProgram and Special-purpose Memory Description Addressing Modes Program MemoryMemory Map Device Interrupt and PTS Vectors Special-purpose MemorySpecial-purpose Memory Addresses Reserved Memory Locations Chip Configuration Bytes CCBs Special-function Registers SFRsSecurity Key Peripheral SFRs Memory-mapped SFRs SFRs EPA and Timer SFRsPeripheral SFRs 8XC196MC Port 2 SFRs Ports 2 and 7 SFRs Peripheral SFRs 8XC196MD Serial I/O Port SFRs Peripheral SFRs 8XC196MHPort 0 and 2 SFRs Port 1 SFRs Address Register File Memory Map Device and Hex Address Range Description Addressing Modes Register File Memory AddressesGeneral-purpose Register RAM Stack Pointer SP CPU Special-function Registers SFRs CPU SFRsAddress High Odd Byte Low Even Byte 00FFH Windowing8XC196MC,MD 02FFH 01FFH WSR Value for Peripherals Selecting a WindowWSR Bit Function Number 10. Selecting a Window of the Upper Register File Addressing a Location Through a Window Peripheral SFRs 11. Windows12. Windowed Base Addresses Base WSR Value WSR Value for Unsupported Locations Windowing Example 2.1 32-byte Windowing Example2.2 64-byte Windowing Example 2.3 128-byte Windowing Example ?WSR Using the Linker Locator to Set Up a Window This listing shows the disassembled code LDB WSR, #12H Windowing and Addressing ModesPage Standard and PTS Interrupts Page Overview of Interrupts Chapter Standard and PTS Interrupts Flow Diagram for PTS and Standard Interrupts Interrupt Signals and Registers Interrupt SignalsInterrupt and PTS Control and Status Registers Ptssrv Interrupt Sources and PrioritiesPipend 1FBEH Ptssel Interrupt Controller PTS Service Interrupt Sources, Vectors, and PrioritiesInterrupt Source Mnemonic Name Vector Priority Software Trap Special InterruptsExternal Interrupt Pin Unimplemented Opcode Waveform Generator Protection Circuitry Multiplexed Interrupt Sources Flow Diagram for the Ovrtm Interrupt End-of-PTS Interrupts Interrupt LatencySituations that Increase Interrupt Latency Standard Interrupt Latency Calculating Latency Standard Interrupt Response Time PTS Interrupt Latency PTS Mode Execution Time in State Times Programming the InterruptsExecution Times for PTS Cycles Standard and PTS Interrupts Bit Function Ptssel8XC196MC 8XC196MD COMP2 MC, MD IntmaskCOMP2 EPA2 COMP1 EPA1 COMP3 COMP0 EPA0 Ovrtm Bit Mnemonic Interrupt Standard Vector NMI Extint SPI COMP3 EPA3 COMP4 EPA4 RI1 RI0 TI1 TI0 INTMASK1NMI Extint NMI Extint EPA5 Pimask 8XC196MC 8XC196MDBit Function Number Mnemonic Modifying Interrupt Priorities PimaskOVRTM1 Standard and PTS Interrupts Determining the Source of an Interrupt Intpend 10. Interrupt Pending Intpend Register INTPEND1 11. Interrupt Pending 1 INTPEND1 Register Pipend 12. Peripheral Interrupt Pending Pipend Register Pipend Initializing the PTS Control Blocks Specifying the PTS Count Ptssrv 14. PTS Service Ptssrv Register Selecting the PTS Mode Single Transfer ModePtscon Ptsdst Ptscb + PTS Single Transfer Mode Control BlockPtsdst H Ptsdst L Ptssrc H Ptssrc L Ptscon Ptscount Register Location Function Standard and PTS Interrupts Block Transfer Mode Single Transfer Mode PtscbBlock Transfer Mode Ptscb Ptsblock Ptscb + PTS Block Transfer Mode Control Block 5 A/D Scan Mode PTS A/D Scan Mode Control Block Address Contents A/D Scan Mode Command/Data Table 5.2 A/D Scan Mode Example 5.1 A/D Scan Mode Cycles Ptscount = 04H Command/Data Table ExampleA/D Scan Mode Ptscb Example PTSPTR2 H = 1FH PTSPTR2 L = AAH Serial I/O Modes 5.3 A/D Scan Mode Example10. Command/Data Table Example 11. A/D Scan Mode Ptscb Example PTS Serial I/O Mode Control Block 1 8XC196MC, MD SA1 SA0 MAJPtsvec SA0 † BaudEpareg SA1 8XC196MC, MD, MH USER’S Manual PTS Serial I/O Mode Control Block 2 8XC196MC, MD Port Mask RegisterPort Address Pointer high byte Data PTSCON1Rpar PTS Serial I/O Mode Control Block 8XC196MC, MD Register Location FunctionPortreg 8XC196MC, MD, MH USER’S Manual PTSCB1 PTSCB2 13. Ssio Transmit Mode PTSCBs Txddone = 23. Synchronous SIO Receive Timing Synchronous SIO Receive Mode Example Clrb Rxddone 14. Ssio Receive Mode PTSCBs Standard and PTS Interrupts Rxddone = 25. Asynchronous SIO Transmit Timing 15. Asio Transmit Mode PTSCBs Standard and PTS Interrupts End-Of-PTS Interrupt Save Critical Data Is PTS 27. Asynchronous SIO Receive Timing Asynchronous SIO Receive Mode Example 16. Asio Receive Mode PTSCBs Samptime = 01HPortreg H = 1FH P2PIN Standard and PTS Interrupts End-Of-PTS Interrupt Ports Page I/O Ports Overview Device I/O PortsPort Bits Type Direction Associated Peripherals INPUT-ONLY Ports 1 MC, MD only Standard Input-only Port Pins P1PIN MC, MD Standard Input-only Port OperationInput-only Port Registers 1FDAH MH Bidirectional Ports 1 MH ONLY, 2, 5, and 7 MD only Standard Input-only Port Considerations Port Pin Special-function Associated Signals Bidirectional Port Pins Bidirectional Port Control and Status Registers Bidirectional Port Operation Ports Bidirectional Port Structure Bidirectional Port Pin Configurations Logic Table for Bidirectional Ports in I/O ModeSfdir 8XC196MC, MD, MH USER’S Manual Bidirectional Port Pin Configuration Example Control Register Values for Each ConfigurationPort Configuration Example HZ1 Bidirectional Port Considerations P5.1/INST 12. Ports 3 and 4 Control and Status Registers Ports 3 and 4 PinsPort Pins Special-function Bidirectional Ports 3 and 4 ADDRESS/DATA BUS Address/Data Bus Ports 3 and 4 Structure Bidirectional Ports 3 and 4 Address/Data Bus Operation 13. Logic Table for Ports 3 and 4 as Open-drain I/O Using Ports 3 and 4 as I/ODesign Considerations for Ports 3 Standard OUTPUT-ONLY Port 15. Output-only Port Control Register Configuring Output-only Port Pins14. Standard Output-only Port Pins Output-only Port Operation OP1 OP0 Reset State 0000HWgoutput Port Address 1FC0H Wgoutput Port Reset State 0000HPage Serial I/O SIO Port Page Serial I/O SIO Port Functional Overview SIO Block Diagram Serial I/O Port Signals and Registers Serial Port SignalsSerial Port Control and Status Registers P1DIR 1F9BH P1PIN 1F9FHP1REG 1F9DH Serial Port Modes Mode Synchronous Modes Modes 0 Mode 0 Timing Asynchronous Modes Modes 1, 2, Serial Port Frames for Mode Multiprocessor Communications Mode 2 and 3 Timings SP xCON Address 1F83H, 1F8BH = 0-1 8XC196MH Configuring the Serial Port PinsProgramming the Serial Port Programming the Control Register Bit Function BV9 BV8 Programming the Baud Rate and Clock SourceClksrc BV7 Bclk Baudvalue = E82BH SPxBAUD Values When Using XTAL1 at 16 MHzEnabling the Serial Port Interrupts 80CFH Determining Serial Port Status RPE/RB8 TXERPE/RB8 8XC196MC, MD, MH USER’S Manual Frequency Generator Page Chapter Frequency Generator Frequency Generator Signal Frequency Generator Control and Status RegistersPort Frequency Freqgen Configuring the OutputProgramming the Frequency Generator Programming the Frequency Determining the Current Value of the Down-counter Application ExampleFreqcnt Frequency Generator 0FAH Xmitbuf Dsb Bufsize Block of data to send Shiftreg Stb temp,freqgen0 Into freq gen Frequency Generator Page Waveform Generator Page Waveform Generator Functional Overview Chapter Waveform Generator Waveform Generator Block Diagram Waveform Generator Signals and Registers Waveform Generator SignalsWaveform Generator Control and Status Registers Timebase Generator Waveform Generator Operation Control and Protection Circuitry Phase Driver Channels Protection Circuitry Register Buffering and Synchronization Operating Modes Step Center-aligned Modes Edge-aligned Modes Register UpdatesEvent Mode Operation in Center-aligned and Edge-aligned Modes Center-aligned Modes Counter Operation Center-aligned Modes Center-aligned Modes Output Operation Edge-Aligned Modes Edge-aligned Modes Counter Operation Configuring the Outputs Output ConfigurationProgramming the Waveform Generator OP1 Wgoutput Waveform GeneratorOP1 OP0 Sync PE7 PE6 8XC196MC, MD, MH USER’S Manual 8XC196MC, MD 8XC196MH Bit Function Number Mnemonic WgprotectF0H E0H 150 Reload Specifying the Carrier Period and Duty CycleWgreload Reload 1FC2H,1FC4H,1FC6H Wgcomp Address Wgcontrol DT7 DT6 DT5 DT4 DT9 DT8 DT3 DT2 DT1 DT0Wgcounter = Wgreload Xxxxh Determining the Waveform GENERATOR’S StatusEnabling the Waveform Generator Interrupts Wgcounter Wgcomp Design ConsiderationsDead Time and Duty Cycle Wgcount WGCOUNT= Programming Example Ph3 Dsw P6.4,5 config Waveform Generator Temp1,WGOUTPUT0 Now store it Ret Demo board PI interrupt Page Pulse-width Modulator Page PWM Functional Overview Chapter PULSE-WIDTH Modulator PWM Signals PWM Signals and Registers PWM Operation PWM Control and Status RegistersPEx Pin Output Programming the Frequency and Period E6HFFH Pwmperiod PWM Output Frequencies Fpwm Pwmperiod + Programming the Duty Cycle Sample Calculations Reading the Current Value of the Down-counterPWM xCONTROL Address 10-3 Pwmcount PWM Output Alternate Port Function PWM Output Enabled WhenEnabling the PWM Outputs PWM Output Alternate Functions Waveform Generator Output Configuration Wgoutput Register Generating Analog Outputs D/A Buffer Block Diagram Event Processor Array EPA Page COMP30 EPA Functional OverviewEPA Channels Device Capture/Compare Channels Compare-only Channels EPA and Timer/Counter Signals EPA and TIMER/COUNTER Signals and Registers EPA Control and Status Registers P1PIN 1FA9H P0PIN 1FA8H T1RELOAD TIMER/COUNTER Functional OverviewTIMER1 1F7AH TIMER2 1F7EH EPA Timer/Counters Quadrature Clocking Modes Cascade Mode Timer 2 Only T1DIR State of Xinternal State of Yinternal Count Direction EPA Channel Functional Overview Quadrature Mode Timing and Count A Single EPA Capture/Compare Channel Operating in Capture Mode EPA Simplified Input-capture Structure EPAxCON.0 Action Taken When a Valid Edge OccursOverwrite Bit Status Action Taken When a Valid Edge Occurs EPA Overruns Operating in Compare Mode Preventing EPA OverrunsGenerating a Low-speed PWM Output Generating the Highest-speed PWM Output Programming the EPA and TIMER/COUNTERS Configuring the EPA and Timer/Counter SignalsProgramming the Timers Prescaler Divisor Resolution † T1CONTROLClock Source Direction Source T2CONTROL Prescaler Resolution † Example EPA Control Register Settings for Channels 1, 3, or Mode WGR ROT ON/RTProgramming the Capture/Compare Channels = 0, 2 = 1, 3 Capture Mode EventCompare Mode Action EPAxCON = 0-1 8XC196MH x = 0-3 8XC196MC x = 0-5 8XC196MD For EPA capture/compare channels 1, 3 EPA xCON Address= 0, 2 For EPA capture/compare channels 0, 2 Compare Mode RT Capture Mode on WGR ROT = 0-3 8XC196MC, MH = 0-5 8XC196MD Reset State 00HProgramming the Compare-only Channels Comp xCON Address Enabling the EPA Interrupts Determining Event Status Analog-to-digital Converter PageNum-38 Angnd 12.1 A/D Converter Functional Overview A/D Control and Status Registers 12.2 A/D Converter Signals and RegistersA/D Converter Pins Port Pin Signal Description P1PIN MC,MD 12.3 A/D Converter Operation Programming the A/D Converter Programming the A/D Test Register AdtestOFF1 OFF0 Adresult Write Programming the A/D Time Register Adtime Programming the A/D Command Register ACH3 ACH2 ACH1 ACH0 AdcommandM1 M0 Mode Enabling the A/D Interrupt Determining A/D Status and Conversion Results Adresult ReadADRLT90 Idealized A/D Sampling Circuitry Designing External Interface Circuitry Minimizing the Effect of High Input Source Resistance Suggested A/D Input Circuit Using Mixed Analog and Digital Inputs Understanding A/D Conversion Errors 12-14 Ideal A/D Conversion Characteristic 10. Actual and Ideal A/D Conversion Characteristics 12-17 11. Terminal-based A/D Conversion Characteristic Minimum Hardware Considerations Page Minimum Required Signals RESET#Minimum Connections 13.1.2 I/O Port Pin Connections I/O Port Configuration GuidePort Where to Find Configuration Information Unused Inputs Minimum Hardware Connections Noise Protection Tips Applying and Removing Power On-chip Oscillator Circuit ON-CHIP Oscillator Circuitry External Crystal Connections External Clock Connections Using AN External Clock Source Reset Timing Sequence Resetting the Device DRO GenconRsts DR0 Rsts Internal Reset Circuitry Generating an External Reset 10. Minimum Reset Circuit Generating Wait States Issuing the Reset RST InstructionEnabling the Watchdog Timer Issuing an Illegal Idlpd Key Operand 1EH A1H Selecting the Watchdog Reset Interval 8XC196MH onlyFirst Byte Second Byte Reset Interval 1EH E1HPage Special Operating Modes Page Clkout Special Operating Mode Signals and RegistersOperating Mode Control Signals Port Pin Signal Type Description CCR0 Operating Mode Control and Status RegistersPort Pin Signal Type Description Name ONCE# P1REG MH 1F9DH Reducing Power ConsumptionP1MODEMH P7MODEMD 1FD1H Clock Control During Power-saving Modes Idle Mode Enabling and Disabling Powerdown Mode Powerdown Mode Driving the VPP Pin Low Entering Powerdown ModeExiting Powerdown Mode Generating a Hardware Reset Asserting the External Interrupt Signal Selecting R1 and C1 External RC Circuit Typical Voltage on the VPP Pin While Exiting Powerdown Once Mode Reserved Test Modes Page Interfacing with External Memory Page ADV# External Memory Interface Signals and RegistersExternal Memory Interface Signals Signal Port Pin Type Description Name CCR1.2 Buswidth Bytes AccessedBHE# AD0 CCR0.1 Signal Port Pin EA#WR# Register Address Description Mnemonic External Memory Interface RegistersWRH# WRL# Chip Configuration Registers and Chip Configuration Bytes P5REG = 11XX XxxxbBHE#/WRH# † 15-6 IRC2 IRC1 IRC0 CCR0LOC1 LOC0 IRC1 IRC0 ALE BW0 LOC1 LOC0 CCR0 ALEBW1 BW0 CCR1 WDE BW1 IRC2WDE CCR1 BUS Width and Multiplexing Multiplexing and Bus Width Options Buswidth Timing Diagram 8XC196MC, MD Buswidth Signal Timing Definitions Symbol DefinitionTiming Requirements for Buswidth 15.3.2 16-bit Bus Timings Timings for 16-bit Buses 15.3.3 8-bit Bus Timings Timings for 8-bit Buses Wait States Ready Control 15-18 Ready Timing Diagram One Wait State 8XC196MC, MD Address Valid to Ready Setup Bus-control Mode Bus-control Signals CCR0.3 CCR0.2 BUS-CONTROL ModesBus-control Modes BHE# WR# AD0 Standard Bus-control Mode ALE OE# WE# RD# WR# CS# Buswidth CS# Eprom RAMOE# WE# RD# WR# 14. Write Strobe Mode Write Strobe Mode OE# OE# WE# RD# WRH# WRL# 15 -bit System with Writes to Byte-wide RAMs 16. Address Valid Strobe Mode Address Valid Strobe Mode 18 -bit System with Flash OE# RD# Eprom 20. Timings of Address Valid with Write Strobe Mode Address Valid with Write Strobe Mode WE# CS# System BUS AC Timing SpecificationsVCC Buswidth WRH# WRL# CS# 22. System Bus Timing AC Timing Definitions Explanation of AC SymbolsAC Timing Symbol Definitions Signals External Memory Systems Must Meet These Specifications Address Setup to ALE/ADV# Low Microcontroller Meets These Specifications 15-35 Page Programming Nonvolatile Memory Page Programming Methods Programming the Nonvolatile Memory Otprom Memory MAP Address Range Description Hex Security FeaturesControlling Access to Internal Memory C196Mx Otprom Memory Map Read Protect Write Protect Protection Status Controlling Access to the Otprom During Normal OperationMemory Protection for Normal Operating Mode Controlling Access to the Otprom During Programming Modes Memory Protection Options for Programming Modes Security KeyPccb CCB Controlling Fetches from External Memory Uprom Programming Values and Locations for Slave Mode UsfrTo set this bit Write this value To this location BitBitFunction Number Mnemonic Programming Pulse WidthPpwvalue PPW Ppwvalue = Modified QUICK-PULSE AlgorithmExample Ppwvalue Calculations 8XC196MC, MD 8XC196MH Two 250-µs pulses required Modified Quick-pulse Algorithm Special Program Port Pin Programming Mode Pins PACT# PROG#AINC# Cpver Selecting the Programming Mode Entering Programming ModesPmode Values Power-up and Power-down Sequences Power-up SequencePower-down Sequence Reading the Signature Word and Programming Voltages Slave Programming Mode Location Value Slave Programming Circuit and Memory MapDevice Signature Word and Programming Voltages Device Signature Word Programming VCC Slave Programming Mode Memory Map Operating EnvironmentDescription Address Comments CCR1, CCR0 LOC1 LOC0 IRC1 IRC0 WDE BW1 IRC2Bit Mnemonic Function Slave Programming Routines Address/Command Decoding Routine Program Word Routine Program Word Waveform 10. Dump Word Routine Timing Mnemonics 10. Timing MnemonicsMnemonicDescription Auto Programming Mode Auto Programming Circuit and Memory MapMnemonic Description 12. Auto Programming Circuit 11 XC196MC/MD Auto Programming Memory Map Address Internal Address Using Output fromAddress Internal Address Using Auto Programming Routine 13. Auto Programming Routine Auto Programming Procedure Pccb and Uprom Programming 8XC196MH only ROM-dump Mode 14. Pccb and Uprom Programming Circuit PMODE30 0DH Pins Pccb Programming Uprom ProgrammingRUN-TIME Programming 13. Pccb and Uprom Programming Values 15. Run-time Programming Code Example Page Instruction Set Reference Page Appendix a Instruction SET Reference Opcode Table A-1. Opcode Map Left Half Table A-1. Opcode Map Right Half Table A-2. Processor Status Word PSW Flags Value of Bits Shifted OffInstruction Quotient Stored Flag Set if Quotient is Table A-4. PSW Flag Setting Symbols Symbol DescriptionInstruction Jumps to Destination if Continues if Variable Description Table A-5. Operand Variables C V VT ST PSW Flag SettingsTable A-6. Instruction Set Mnemonic Operation Instruction Format Dest ← Dest and SRCAndb Count PTRS, Cntreg Dest Count ← Cntreg Loop Srcptr ← Ptrs DstptrDstptr ← Srcptr Ptrs ← Srcptr + Count ← Count Clear BYTE. Clears the value Mnemonic Operation Instruction Format Dest MOD SRC ← Dest MOD SRC Djnzw Decrement and Jump if not Zero Djnz Decrement and Jump if not Zero EXT SIGN-EXTEND Integer Into Long Dpts Disable Peripheral TransactionEpts Enable Peripheral Transaction Epts Extb SIGN-EXTEND SHORT-INTEGER Into Increment BYTE. Increments the value Byte operand by JGE Jump if Signed Greater than or JLE Jump if Signed Less than or Equal Negative flag is set, this instruction adds JNV Jump if Overflow Flag is Clear Jnvt Jump if OVERFLOW-TRAP Flag is JVT Jump if OVERFLOW-TRAP Flag is SET Load Byte SIGN-EXTENDED. Sign Mulb MUL Mulub Mulu SRC, Dest Integer operand Dest ← Dest or SRC Dest ← not Dest PSW/INTMASK ← SP INTMASK1/WSR ← SP SP ← INTMASK1/WSR INTMASK1 ← SP ← PSW/INTMASK PSW/INTMASK ← Scall Wreg, #count SHR Range of 0 to 31 1FH, inclusive. If Shral Arithmetic Right Shift Double Skip Shrl Logical Right Shift DOUBLE-WORD SUB Rightmost operand Subcb Subtract Bytes with Borrow DEST, SRC SubbSubc Subtract Words with Borrow DEST, SRC Subc Index and #MASK = Offset × Offset + Tbase = DestTijmp TBASE, INDEX, #MASK Dest ← Dest XOR SRC XOR Decb Extb Incb Shrb Shlb Shrab Table A-7. Instruction OpcodesHex Code Instruction Mnemonic Clrb Notb Negb Hex Code Hex Code 8XC196MC, MD, MH USER’S Manual EF Lcall Dpts Epts DIV/DIVB/MUL/MULB Note Table A-8. Instruction Lengths and Hexadecimal Opcodes Arithmetic Group Direct Immediate Indirect Indexed MnemonicSubc Subcb Logical Direct Immediate Indirect Jump Direct Stack Direct Immediate Indirect Indexed MnemonicOpcode Length Data Direct Call Direct Immediate Indirect Indexed Mnemonic Length OpcodeConditional Jump Direct Immediate Mnemonic Direct Immediate Indirect Shift Mnemonic Direct Immediate Indirect IndexedSpecial Mnemonic Direct Immediate Indirect PTS Mem Reg Table A-9. Instruction Execution Times in State TimesArithmetic Group Indirect Normal Autoinc Short Long Reg Mem Mnemonic Direct Immed Normal Autoinc Short Long Reg Mem DIV Divb Divu DivubLogical Stack Register Indirect Normal Autoinc ShortReg Mem Ljmp Sjmp Tijmp Autoinc Short Long RegLDB Ldbse Ldbze STB XCH Xchb Autoinc Short Long Call Memory Indirect Indexed Mnemonic Direct Normal Autoinc Short LongConditional Jump Mnemonic NOP RST Setc Skip Shift Mnemonic DirectIndirect Indexed Clrc Clrvt IdlpdPage Signal Descriptions Page New Name Signal Name ChangesFunctional Groupings of Signals Table B-1. Signal Name Changes Table B-2 XC196MC Signals Arranged by Functional Categories U8XC196MC Figure B-1 XC196MC 64-lead Shrink DIP Sdip Package X8XC196MC Figure B-2 XC196MC 84-lead Plcc Package Figure B-3 XC196MC 80-lead Shrink EIAJ/QFP Package P7.7/FREQOUT Table B-3 XC196MD Signals Arranged by Functional Categories X8XC196MD Figure B-4 XC196MD 84-lead Plcc Package Figure B-5 XC196MD 80-lead Shrink EIAJ/QFP Package Table B-4 XC196MH Signals Arranged by Functional Categories EA# Extint NMI ONCE# RESET# XTAL1 XTAL2P2.7/SCLK1#/BCLK1 X8XC196MH Figure B-6 XC196MH 64-lead Shrink DIP Sdip Package Figure B-7 XC196MH 84-lead Plcc Package Figure B-8 XC196MH 80-lead Shrink EIAJ/QFP Package Signal Descriptions Table B-6. Signal Descriptions Table B-5. Description of Columns of Table B-6Column Heading Description Name BCLK10 CCR0.1 CCR1.2 BuswidthCOMP1/P2.5/PACT#, COMP2/P2.6/CPVER, COMP3/P2.7MC, MD Command that invoked the power-saving mode System using a clip-on emulator P5.7/BUSWIDTH Slave programming Auto programmingPMODE.30 Programming Start SCLK10# Shift Clock 0 MH only Default Conditions Functions RESET# Active Table B-7. Definition of Status SymbolsTable B-8 XC196MC and MD Default Signal Conditions Port Signals Alternate During Upon RESET# PWM0 WK0 NMI WK0 RESET#WG2 WK1 WG3 WK1 Alternate During Upon Table B-9 XC196MH Default Signal ConditionsRESET# Port Signals Osc output Registers Page Table C-1. Modules and Related Registers CPU8XC196MC, MH, x = Table C-2. Register Name, Address, and Reset Status Xxxx EPA5TIME MD Xxxx EPA2TIME MC, MDXxxx EPA3TIME MC, MD Xxxx EPA4TIME MD P5REG MC, MD P7PIN MDXxxx P1REG MH 1FFD Usfr MH Xxxx Watchdog Xxxx TIMER1TIMER2 Usfr MC, MD Adcommand Adresult Read Adresult Write Adtest Adtime CCR0 ALE CCR1 IRC2 IRC1 IRC0 Comp xCON Address Table C-3 = 0-3 8XC196MC, MH COMPxCON For EPA capture/compare channels 0, 2 Comp xTIME Address Table C-3. COMPxTIME Addresses and Reset ValuesRegister Address Reset Value COMPxTIME EPAxCON = 0-3 8XC196MC x = 0-5 8XC196MD EPAxCON Address Table C-4 = 0-1 8XC196MH = 0-3 8XC196MC = 0-5 8XC196MD Table C-4. EPAxCON Addresses and Reset Values EPAxTIME = 0-1 8XC196MH x = 0-3 8XC196MC x = 0-5 8XC196MD Table C-5. EPAxTIME Addresses and Reset ValuesEPA Timer Value EPAxTIME Freqcnt Freqgen Gencon OVRTM† Intmask INTMASK1 Intpend INTPEND1 One OnesregOnesreg Ffffh = 2, 5 M Table C-6. PxDIR Addresses and Reset ValuesPxDIR = 1 MH PIN7 PIN6 PIN5 PIN4 Table C-7. PxMODE Addresses and Reset ValuesPxMODE = 1 MH = 2, 5 Mx 8XC196MC, MD Table C-8. Special-function Signals for Ports 1, 2, 5Pin Special-function Signal Port PxPIN Table C-9. PxPIN Addresses and Reset Values = 2-5 M Table C-10. PxREG Addresses and Reset ValuesPxREG PxREG = 2-5 8XC196MC = 2-5, 7 8XC196MD x = 1-5 8XC196MH Pimask Pimask Pipend Pipend PPW150 Ppwvalue PPW PSW PSWPSE PSW Ptssel Ptssrv Pwmcount Pwmperiod PWM xCONTROL Address 1FB0H, 1FB2H PWMxCONTROL SBUFxRX SBUFxRX Address 1F80H, 1F88H = 0-1 8XC196MH8XC196MH Data Received Bit SBUFxTX Sbuf xTX Address 1F82H, 1F8AH = 0-1 8XC196MH8XC196MH Data to Transmit Bit 150 Stack Pointer Stack Pointer SPxBAUD SPxCON Address 1F83H, 1F8BH = 0-1 8XC196MH SPxCON SPxSTATUS T1CONTROL Timer 1 Reload Value T1RELOADT1RELOAD T2CONTROL TIMERx Timer Address 1F7AH1F7EH Usfr Watchdog Watchdog0AH WGCOMPx Wgcontrol Wgcounter Wgoutput Port Wgoutput Waveform Generator Wgoutput Waveform Generator Output Values Output Polarities WG x# Table C-11. Output Configuration Wgprotect Wgreload 00E0-00FFH 00C0-00FFH WSRByte Windows Register Mnemonic 00E0-00FFH 00C0-00FFH 0080-00FFH Location PWM1CONTROL 1FB2H 7DH T2CONTROL 1F7CH 7BH 00FCH 3DH 1EH TIMER1 † 1F7AH 00FAH1EH 00FAH TIMER2 † 1F7EH 7BH 00FEH 3DH WGCOMP1 1FC2H PWM0CONTROL 1FB0H 7DH Zeroreg ZeroregZero Page Glossary Page Glossary Characteristic DOUBLE-WORD LONG-INTEGER LSB Otprom PTS PWM SFR Special interrupt WDT Page Index Page Index Index-2 Index-3 Index-4 Index-5 Index-6 Index-7 Index-8 Index-9 Index-10 Index-11 Index-12 Index-13 Index-14