Intel 8XC196MC, 8XC196MD, 8XC196MH 5-23, Figure 5-12. Peripheral Interrupt Pending (PI_PEND) Register

5-23
STANDARD AND PTS INTERRUPTS
PI_PEND Address:
Reset State: 1FBEH AAH
When hardware detec ts a pending periphera l or timer interrup t, it sets the correspo nding bit in the
interrupt pending (INT_PEND o r INT_PEND1) registers and the perip heral interrupt pending
(PI_PEND) register. When the vector is taken, t he hardware clears the INT_PEND/ INT_PEND1
pending bit. Reading this reg ister clears all the PI_PEND b its. Software can generate an interrupt by
setting a PI_PEND bit.
7 0
8XC196MC ———WG —OVRTM2 — OVRTM1
7 0
8XC196MD — COMP5 —WG —OVRTM2 — OVRTM1
7 0
8XC196MH —SP1—SP0 —OVRTM2 — OVRTM1
Bit
Number Bit Mnemonic Function
7, 5, 3, 1 — Reserved. These bits are undefined.
6 — (MC) Reserved. This bit is und efined.
COMP5 (MD) EPA Compare Channel 5
When set, this bit indica tes a pending EPA compare channel 5 interrupt.
The EPA compare channel 5 and the waveform generator interru pt s are
associated with the peripheral interrupt (PI). Setting INT_ M ASK1 .5
enables PI. Setting PI_MASK. 6 enables COMP5.
SP1 (MH) Serial Port 1 Error
When set, this bit indicates a pending serial port 1 erro r interrupt.
The serial port 1 and 0 error interrupts are associated with the serial p ort
interrupt (SPI). Setting INT_MASK 1.4 enables SPI. Setting PI_MAS K.6
enables SP1.
4 WG (MC, MD) Waveform Generator
When set, this bit indicates a pending waveform genera tor interrupt.
The waveform generator and the EPA compare channe l 5 interru pt s are
associated with the peripheral interrupt (PI). Setting INT_ M ASK1 .5
enables PI. Setting PI_MASK. 5 enables WG.
SP0 (MH) Serial Port 0 Error
When set, this bit indicates a pending serial port 0 erro r interrupt.
The serial port 0 and 1 error interrupts are associated with the serial p ort
interrupt (SPI). Setting INT_MASK 1.4 enables SPI. Setting PI_MAS K.4
enables SP0.
Figure 5-12. Peripheral Interrupt Pending (PI_PEND) Register