Intel 8XC196MC, 8XC196MD, 8XC196MH 5-29, Figure 5-16. PTS Control Block Single Transfer Mode (Continued)

5-29
STANDARD AND PTS INTERRUPTS
The PTSCB in Table 5-5 defines nine PTS cycles. Each cycle moves a single word from location
20H to an external memory location. The PTS transfers the first word to locatio n 6000H. Then it
increments and updates the destination address and decrements the PTSCOUNT register; it does
not increment the source address. When the second cyc le begins, the PTS moves a second word
from location 20H to location 6002H. When PTSCOUNT equals zero, the PTS will have filled
locations 6000–600FH, and an end-of-PTS interrupt is generated.
Register Location Function
PTSCON PTSCB + 1 PTS Control Bits
M2:0 PTS Mode
M2 M1 M0
1 0 0 single transfer mode
BW Byte/Word Transfer
0 = word transfer
1 = byte transfer
SU†Update PTSSRC
0 = reload origin al PTS source address after each byte or word
transfer
1 = reta in curre nt PTS source address afte r each byte or word
transfer
DU†Update PTSDST
0 = reload original PTS destination address afte r each byte or
word transfer
1 = re ta in curre nt PTS destin atio n addre ss afte r each byte or
word transfer
SI†PTSSRC Autoincrement
0 = do not increment the contents of PTSSRC after each b yte
or word transfer
1 = increment the contents of PTSSRC after each byte or word
transfer
DI†PTSDST Autoincrement
0 = do not increment the contents of PTSDST after each byte
or word transfer
1 = increment the contents of PTSDST after each byte or word
transfer
PTSCOUNT PTSCB + 0 Consecutive Word or Byte Transfers
Defines the number of words or bytes that will be transferre d during the
single transfer routine. Each word or byte transfer is one PT S cycle.
Maximum value is 255.
†The DU/DI bits and SU/SI bits are paired in single transfer mode. Each pair must be set or cleared
together. However, the two pairs, DU/DI and SU/SI, need not be equal.
PTS Single Transfer Mode Control Blo ck (Continued)
Figure 5-16. PTS Control Block — Single Transfer Mode (Continued)