15-18 | Intel 8XC196MD, 8XC196MH, 8XC196MC specs

8XC196MC, MD, MH USER’S MANUAL

After the CCB1 fetch, the internal ready control circuitry allows slow external memory devices to increase the length of the read and write bus cycles. If the external memory device is not ready for access, it pulls the READY signal low and holds it low until it is ready to complete the oper- ation, at which time it releases READY. While READY is low, the bus controller inserts wait states into the bus cycle.

The internal ready control bits, CCR0.5, CCR0.4, and CCR1.1 shown in Figures 15-1 and 15-2, define the maximum number of wait states (0, 1, 2, 3, or infinite) that will be inserted into the bus cycle. While READY is low, wait states are inserted into the bus cycle until the programmed number of wait states is reached. If READY is pulled high before the programmed number of wait states is reached, no additional wait states will be inserted into the bus cycle.

If you choose the infinite wait states option, you must keep P5.6 configured as the READY signal. Also, be sure to add external hardware to count wait states and pull READY high within a spec- ified time. Otherwise, a defective external device could tie up the address/data bus indefinitely.

Setup and hold timings must be met when using the READY signal to insert wait states into a bus cycle (see Figures 15-8 and 15-9, and Table 15-5). Because a decoded, valid address is used to generate the READY signal, the setup time is specified relative to the address being valid. This specification, TAVYV, indicates how much time the external device has to decode the address and assert READY after the address is valid. As shown in Figure 15-9, the 8XC196MH has an addi- tional READY setup timing specification. This specification, TLLYV, indicates how much time an external device has to deassert the READY signal after ALE falls.

The READY signal must be held low until the minimum TCLYX timing specification is met. Do not exceed the maximum TCLYX or TLLYX specification or additional (unwanted) wait states might be added. Refer to the datasheets for the current TAVYV , TCLYX, and TLLYX specifications.

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Intel 8XC196MD, 8XC196MH, 8XC196MC manual 15-18

Contents

8XC196MC, 8XC196MD, 8XC196MH Microcontroller User’ Manual We Value Your Opinion Page 8XC196MC, 8XC196MD, 8XC196MH Microcontroller User’s Manual Intel Corporation Contents Chapter Memory Partitions Contents 8XC196MC, MD, MH USER’S Manual Functional Overview Programming the Frequency Generator PWM Signals and RegistersApplication Example Programming the Waveform Generator Chapter Event Processor Array EPA Chapter Minimum Hardware Considerations Chapter Programming the Nonvolatile Memory Appendix C Registers Glossary Index Figures 10-5 15-9 Ready Timing Diagram One Wait State 8XC196MH 15-21 Tables 11-12 16-7 Pmode Values Guide to This Manual Page Chapter Guide to this Manual Manual Contents Special Operating Modes Assert and deassert Notational Conventions and Terminology Numbers Related Documents Handbooks and Product Information Application Notes, Application Briefs, and Article ReprintsTitle Order Number MCS 96 Microcontroller Datasheets Automotive MCS 96 Microcontroller Datasheets Commercial/Express This Page Left Intentionally Blank Guide to this Manual This Page Left Intentionally Blank World Wide Web Technical SupportProduct Literature Page Architectural Overview Page Typical Applications Microcontroller Features Functional Overview Features of the 8XC196Mx Product FamilyOtprom SIO PWM PTS EPA PWM WDT SIO ROMCPU RAM CPU Control Register FileRegister Arithmetic-logic Unit Ralu Instruction Format Code Execution Memory Interface Unit Interrupt Service Clock Circuitry Internal Timing State Times at Various Frequencies Internal Peripherals Serial I/O SIO Port 1 I/O Ports Pulse-width Modulator PWM Event Processor Array EPA and Timer/CountersFrequency Generator Waveform Generator Reducing Power Consumption Watchdog TimerTesting the Printed Circuit Board Analog-to-digital Converter Programming the Nonvolatile Memory Programming Considerations Page Operand Type Definitions Overview of the Instruction SETOperand Type No. Signed Possible Values Addressing Restrictions Byte Operands BIT OperandsSHORT-INTEGER Operands Word Operands DOUBLE-WORD Operands Integer Operands Converting Operands LONG-INTEGER OperandsConditional Jumps Floating Point Operations Addressing Modes Immediate Addressing Direct AddressingIndirect Addressing Definition of Temporary Registers Indirect Addressing with Autoincrement Indexed AddressingIndirect Addressing with the Stack Pointer Short-indexed Addressing Zero-indexed Addressing Long-indexed Addressing Assembly Language Addressing Mode Selections Using RegistersSoftware Standards and Conventions Linking Subroutines Addressing 32-bit Operands Software Protection Features and Guidelines 8XC196MC, MD, MH USER’S Manual Memory Partitions Page Memory Partitions External Devices Memory or I/OProgram and Special-purpose Memory Memory Map Program MemoryDevice Description Addressing Modes Special-purpose Memory Addresses Special-purpose MemoryReserved Memory Locations Interrupt and PTS Vectors Chip Configuration Bytes CCBs Special-function Registers SFRsSecurity Key Peripheral SFRs Memory-mapped SFRs Peripheral SFRs 8XC196MC EPA and Timer SFRsPort 2 SFRs SFRs Ports 2 and 7 SFRs Peripheral SFRs 8XC196MD Port 0 and 2 SFRs Peripheral SFRs 8XC196MHPort 1 SFRs Serial I/O Port SFRs Address Register File Memory Map General-purpose Register RAM Register File Memory AddressesStack Pointer SP Device and Hex Address Range Description Addressing Modes CPU Special-function Registers SFRs CPU SFRsAddress High Odd Byte Low Even Byte 8XC196MC,MD Windowing02FFH 01FFH 00FFH WSR Selecting a WindowBit Function Number WSR Value for Peripherals 10. Selecting a Window of the Upper Register File Addressing a Location Through a Window 12. Windowed Base Addresses 11. WindowsBase WSR Value WSR Value for Peripheral SFRs 2.2 64-byte Windowing Example 2.1 32-byte Windowing Example2.3 128-byte Windowing Example Unsupported Locations Windowing Example ?WSR Using the Linker Locator to Set Up a Window This listing shows the disassembled code LDB WSR, #12H Windowing and Addressing ModesPage Standard and PTS Interrupts Page Overview of Interrupts Chapter Standard and PTS Interrupts Flow Diagram for PTS and Standard Interrupts Interrupt Signals and Registers Interrupt SignalsInterrupt and PTS Control and Status Registers Pipend 1FBEH Interrupt Sources and PrioritiesPtssel Ptssrv Interrupt Controller PTS Service Interrupt Sources, Vectors, and PrioritiesInterrupt Source Mnemonic Name Vector Priority External Interrupt Pin Special InterruptsUnimplemented Opcode Software Trap Waveform Generator Protection Circuitry Multiplexed Interrupt Sources Flow Diagram for the Ovrtm Interrupt End-of-PTS Interrupts Interrupt LatencySituations that Increase Interrupt Latency Standard Interrupt Latency Calculating Latency Standard Interrupt Response Time PTS Interrupt Latency PTS Mode Execution Time in State Times Programming the InterruptsExecution Times for PTS Cycles Standard and PTS Interrupts 8XC196MC Ptssel8XC196MD Bit Function COMP2 EPA2 COMP1 EPA1 COMP3 COMP0 EPA0 Ovrtm IntmaskBit Mnemonic Interrupt Standard Vector COMP2 MC, MD NMI Extint INTMASK1NMI Extint EPA5 NMI Extint SPI COMP3 EPA3 COMP4 EPA4 RI1 RI0 TI1 TI0 Pimask 8XC196MC 8XC196MDBit Function Number Mnemonic Modifying Interrupt Priorities PimaskOVRTM1 Standard and PTS Interrupts Determining the Source of an Interrupt Intpend 10. Interrupt Pending Intpend Register INTPEND1 11. Interrupt Pending 1 INTPEND1 Register Pipend 12. Peripheral Interrupt Pending Pipend Register Pipend Initializing the PTS Control Blocks Specifying the PTS Count Ptssrv 14. PTS Service Ptssrv Register Selecting the PTS Mode Single Transfer ModePtscon Ptsdst H Ptsdst L Ptssrc H Ptssrc L Ptscon Ptscount PTS Single Transfer Mode Control BlockRegister Location Function Ptsdst Ptscb + Standard and PTS Interrupts Block Transfer Mode Single Transfer Mode PtscbBlock Transfer Mode Ptscb Ptsblock Ptscb + PTS Block Transfer Mode Control Block 5 A/D Scan Mode PTS A/D Scan Mode Control Block Address Contents A/D Scan Mode Command/Data Table 5.2 A/D Scan Mode Example 5.1 A/D Scan Mode Cycles A/D Scan Mode Ptscb Example Command/Data Table ExamplePTSPTR2 H = 1FH PTSPTR2 L = AAH Ptscount = 04H 10. Command/Data Table Example 5.3 A/D Scan Mode Example11. A/D Scan Mode Ptscb Example Serial I/O Modes PTS Serial I/O Mode Control Block 1 8XC196MC, MD SA1 SA0 MAJPtsvec Epareg BaudSA1 SA0 † 8XC196MC, MD, MH USER’S Manual PTS Serial I/O Mode Control Block 2 8XC196MC, MD Port Mask RegisterPort Address Pointer high byte Data PTSCON1Rpar PTS Serial I/O Mode Control Block 8XC196MC, MD Register Location FunctionPortreg 8XC196MC, MD, MH USER’S Manual PTSCB1 PTSCB2 13. Ssio Transmit Mode PTSCBs Txddone = 23. Synchronous SIO Receive Timing Synchronous SIO Receive Mode Example Clrb Rxddone 14. Ssio Receive Mode PTSCBs Standard and PTS Interrupts Rxddone = 25. Asynchronous SIO Transmit Timing 15. Asio Transmit Mode PTSCBs Standard and PTS Interrupts End-Of-PTS Interrupt Save Critical Data Is PTS 27. Asynchronous SIO Receive Timing Asynchronous SIO Receive Mode Example 16. Asio Receive Mode PTSCBs Samptime = 01HPortreg H = 1FH P2PIN Standard and PTS Interrupts End-Of-PTS Interrupt Ports Page I/O Ports Overview Device I/O PortsPort Bits Type Direction Associated Peripherals INPUT-ONLY Ports 1 MC, MD only Standard Input-only Port Pins Input-only Port Registers Standard Input-only Port Operation1FDAH MH P1PIN MC, MD Bidirectional Ports 1 MH ONLY, 2, 5, and 7 MD only Standard Input-only Port Considerations Port Pin Special-function Associated Signals Bidirectional Port Pins Bidirectional Port Control and Status Registers Bidirectional Port Operation Ports Bidirectional Port Structure Bidirectional Port Pin Configurations Logic Table for Bidirectional Ports in I/O ModeSfdir 8XC196MC, MD, MH USER’S Manual Bidirectional Port Pin Configuration Example Control Register Values for Each ConfigurationPort Configuration Example HZ1 Bidirectional Port Considerations P5.1/INST Port Pins Special-function Ports 3 and 4 PinsBidirectional Ports 3 and 4 ADDRESS/DATA BUS 12. Ports 3 and 4 Control and Status Registers Address/Data Bus Ports 3 and 4 Structure Bidirectional Ports 3 and 4 Address/Data Bus Operation Design Considerations for Ports 3 Using Ports 3 and 4 as I/OStandard OUTPUT-ONLY Port 13. Logic Table for Ports 3 and 4 as Open-drain I/O 14. Standard Output-only Port Pins Configuring Output-only Port PinsOutput-only Port Operation 15. Output-only Port Control Register Wgoutput Port Address Reset State 0000H1FC0H OP1 OP0 Wgoutput Port Reset State 0000HPage Serial I/O SIO Port Page Serial I/O SIO Port Functional Overview SIO Block Diagram Serial I/O Port Signals and Registers Serial Port SignalsSerial Port Control and Status Registers P1DIR 1F9BH P1PIN 1F9FHP1REG 1F9DH Serial Port Modes Mode Synchronous Modes Modes 0 Mode 0 Timing Asynchronous Modes Modes 1, 2, Serial Port Frames for Mode Multiprocessor Communications Mode 2 and 3 Timings Programming the Serial Port Configuring the Serial Port PinsProgramming the Control Register SP xCON Address 1F83H, 1F8BH = 0-1 8XC196MH Bit Function Clksrc Programming the Baud Rate and Clock SourceBV7 BV9 BV8 Bclk Baudvalue = Enabling the Serial Port Interrupts SPxBAUD Values When Using XTAL1 at 16 MHz80CFH E82BH Determining Serial Port Status RPE/RB8 TXERPE/RB8 8XC196MC, MD, MH USER’S Manual Frequency Generator Page Chapter Frequency Generator Frequency Generator Signal Frequency Generator Control and Status RegistersPort Frequency Programming the Frequency Generator Configuring the OutputProgramming the Frequency Freqgen Determining the Current Value of the Down-counter Application ExampleFreqcnt Frequency Generator 0FAH Xmitbuf Dsb Bufsize Block of data to send Shiftreg Stb temp,freqgen0 Into freq gen Frequency Generator Page Waveform Generator Page Waveform Generator Functional Overview Chapter Waveform Generator Waveform Generator Block Diagram Waveform Generator Signals and Registers Waveform Generator SignalsWaveform Generator Control and Status Registers Timebase Generator Waveform Generator Operation Control and Protection Circuitry Phase Driver Channels Protection Circuitry Register Buffering and Synchronization Operating Modes Event Mode Register UpdatesOperation in Center-aligned and Edge-aligned Modes Step Center-aligned Modes Edge-aligned Modes Center-aligned Modes Counter Operation Center-aligned Modes Center-aligned Modes Output Operation Edge-Aligned Modes Edge-aligned Modes Counter Operation Configuring the Outputs Output ConfigurationProgramming the Waveform Generator OP1 OP0 Sync PE7 Wgoutput Waveform GeneratorPE6 OP1 8XC196MC, MD, MH USER’S Manual F0H WgprotectE0H 8XC196MC, MD 8XC196MH Bit Function Number Mnemonic Wgreload Specifying the Carrier Period and Duty CycleReload 150 Reload 1FC2H,1FC4H,1FC6H Wgcomp Address Wgcontrol DT7 DT6 DT5 DT4 DT9 DT8 DT3 DT2 DT1 DT0Wgcounter = Wgreload Enabling the Waveform Generator Interrupts Determining the Waveform GENERATOR’S StatusWgcounter Xxxxh Dead Time and Duty Cycle Design ConsiderationsWgcount WGCOUNT= Wgcomp Programming Example Ph3 Dsw P6.4,5 config Waveform Generator Temp1,WGOUTPUT0 Now store it Ret Demo board PI interrupt Page Pulse-width Modulator Page PWM Functional Overview Chapter PULSE-WIDTH Modulator PWM Signals PWM Signals and Registers PWM Operation PWM Control and Status RegistersPEx Pin Output Programming the Frequency and Period E6HFFH Pwmperiod PWM Output Frequencies Fpwm Pwmperiod + Programming the Duty Cycle Sample Calculations Reading the Current Value of the Down-counterPWM xCONTROL Address 10-3 Enabling the PWM Outputs PWM Output Alternate Port Function PWM Output Enabled WhenPWM Output Alternate Functions Pwmcount Waveform Generator Output Configuration Wgoutput Register Generating Analog Outputs D/A Buffer Block Diagram Event Processor Array EPA Page EPA Channels EPA Functional OverviewDevice Capture/Compare Channels Compare-only Channels COMP30 EPA and Timer/Counter Signals EPA and TIMER/COUNTER Signals and Registers EPA Control and Status Registers P1PIN 1FA9H P0PIN 1FA8H TIMER1 1F7AH TIMER/COUNTER Functional OverviewTIMER2 1F7EH T1RELOAD EPA Timer/Counters Quadrature Clocking Modes Cascade Mode Timer 2 Only T1DIR State of Xinternal State of Yinternal Count Direction EPA Channel Functional Overview Quadrature Mode Timing and Count A Single EPA Capture/Compare Channel Operating in Capture Mode EPA Simplified Input-capture Structure Overwrite Bit Status Action Taken When a Valid Edge Occurs Action Taken When a Valid Edge OccursEPA Overruns EPAxCON.0 Operating in Compare Mode Preventing EPA OverrunsGenerating a Low-speed PWM Output Generating the Highest-speed PWM Output Programming the EPA and TIMER/COUNTERS Configuring the EPA and Timer/Counter SignalsProgramming the Timers Prescaler Divisor Resolution † T1CONTROLClock Source Direction Source T2CONTROL Prescaler Resolution † Example EPA Control Register Settings for Channels 1, 3, or Mode WGR ROT ON/RTProgramming the Capture/Compare Channels Compare Mode Action Capture Mode EventEPAxCON = 0-1 8XC196MH x = 0-3 8XC196MC x = 0-5 8XC196MD = 0, 2 = 1, 3 = 0, 2 EPA xCON AddressFor EPA capture/compare channels 0, 2 For EPA capture/compare channels 1, 3 Compare Mode RT Capture Mode on Programming the Compare-only Channels = 0-3 8XC196MC, MH = 0-5 8XC196MD Reset State 00HComp xCON Address WGR ROT Enabling the EPA Interrupts Determining Event Status Analog-to-digital Converter PageNum-38 Angnd 12.1 A/D Converter Functional Overview A/D Converter Pins 12.2 A/D Converter Signals and RegistersPort Pin Signal Description A/D Control and Status Registers P1PIN MC,MD 12.3 A/D Converter Operation Programming the A/D Converter Programming the A/D Test Register AdtestOFF1 OFF0 Adresult Write Programming the A/D Time Register Adtime Programming the A/D Command Register M1 M0 Mode AdcommandEnabling the A/D Interrupt ACH3 ACH2 ACH1 ACH0 Determining A/D Status and Conversion Results Adresult ReadADRLT90 Idealized A/D Sampling Circuitry Designing External Interface Circuitry Minimizing the Effect of High Input Source Resistance Suggested A/D Input Circuit Using Mixed Analog and Digital Inputs Understanding A/D Conversion Errors 12-14 Ideal A/D Conversion Characteristic 10. Actual and Ideal A/D Conversion Characteristics 12-17 11. Terminal-based A/D Conversion Characteristic Minimum Hardware Considerations Page Minimum Required Signals RESET#Minimum Connections Port Where to Find Configuration Information I/O Port Configuration GuideUnused Inputs 13.1.2 I/O Port Pin Connections Minimum Hardware Connections Noise Protection Tips Applying and Removing Power On-chip Oscillator Circuit ON-CHIP Oscillator Circuitry External Crystal Connections External Clock Connections Using AN External Clock Source Reset Timing Sequence Resetting the Device Rsts DR0 GenconRsts DRO Internal Reset Circuitry Generating an External Reset 10. Minimum Reset Circuit Enabling the Watchdog Timer Issuing the Reset RST InstructionIssuing an Illegal Idlpd Key Operand Generating Wait States First Byte Second Byte Reset Interval Selecting the Watchdog Reset Interval 8XC196MH only1EH E1H 1EH A1HPage Special Operating Modes Page Operating Mode Control Signals Special Operating Mode Signals and RegistersPort Pin Signal Type Description Clkout Port Pin Signal Type Description Name Operating Mode Control and Status RegistersONCE# CCR0 P1MODEMH Reducing Power ConsumptionP7MODEMD 1FD1H P1REG MH 1F9DH Clock Control During Power-saving Modes Idle Mode Enabling and Disabling Powerdown Mode Powerdown Mode Exiting Powerdown Mode Entering Powerdown ModeGenerating a Hardware Reset Driving the VPP Pin Low Asserting the External Interrupt Signal Selecting R1 and C1 External RC Circuit Typical Voltage on the VPP Pin While Exiting Powerdown Once Mode Reserved Test Modes Page Interfacing with External Memory Page External Memory Interface Signals External Memory Interface Signals and RegistersSignal Port Pin Type Description Name ADV# BHE# AD0 Bytes AccessedCCR0.1 CCR1.2 Buswidth Signal Port Pin EA#WR# WRH# External Memory Interface RegistersWRL# Register Address Description Mnemonic Chip Configuration Registers and Chip Configuration Bytes P5REG = 11XX XxxxbBHE#/WRH# † 15-6 LOC1 LOC0 IRC1 IRC0 ALE BW0 CCR0LOC1 LOC0 IRC2 IRC1 IRC0 CCR0 ALEBW1 BW0 CCR1 WDE BW1 IRC2WDE CCR1 BUS Width and Multiplexing Multiplexing and Bus Width Options Buswidth Timing Diagram 8XC196MC, MD Buswidth Signal Timing Definitions Symbol DefinitionTiming Requirements for Buswidth 15.3.2 16-bit Bus Timings Timings for 16-bit Buses 15.3.3 8-bit Bus Timings Timings for 8-bit Buses Wait States Ready Control 15-18 Ready Timing Diagram One Wait State 8XC196MC, MD Address Valid to Ready Setup Bus-control Mode Bus-control Signals CCR0.3 CCR0.2 BUS-CONTROL ModesBus-control Modes BHE# WR# AD0 Standard Bus-control Mode ALE OE# WE# RD# WR# CS# Buswidth CS# Eprom RAMOE# WE# RD# WR# 14. Write Strobe Mode Write Strobe Mode OE# OE# WE# RD# WRH# WRL# 15 -bit System with Writes to Byte-wide RAMs 16. Address Valid Strobe Mode Address Valid Strobe Mode 18 -bit System with Flash OE# RD# Eprom 20. Timings of Address Valid with Write Strobe Mode Address Valid with Write Strobe Mode VCC Buswidth System BUS AC Timing SpecificationsWRH# WRL# CS# WE# CS# 22. System Bus Timing AC Timing Symbol Definitions Signals Explanation of AC SymbolsExternal Memory Systems Must Meet These Specifications AC Timing Definitions Address Setup to ALE/ADV# Low Microcontroller Meets These Specifications 15-35 Page Programming Nonvolatile Memory Page Programming Methods Programming the Nonvolatile Memory Otprom Memory MAP Controlling Access to Internal Memory Security FeaturesC196Mx Otprom Memory Map Address Range Description Hex Memory Protection for Normal Operating Mode Controlling Access to the Otprom During Normal OperationControlling Access to the Otprom During Programming Modes Read Protect Write Protect Protection Status Memory Protection Options for Programming Modes Security KeyPccb CCB Controlling Fetches from External Memory Uprom Programming Values and Locations for Slave Mode UsfrTo set this bit Write this value To this location Ppwvalue Programming Pulse WidthPPW BitBitFunction Number Mnemonic Example Ppwvalue Calculations Modified QUICK-PULSE Algorithm8XC196MC, MD 8XC196MH Two 250-µs pulses required Ppwvalue = Modified Quick-pulse Algorithm Special Program Port Pin Programming Mode Pins AINC# PROG#Cpver PACT# Selecting the Programming Mode Entering Programming ModesPmode Values Power-up and Power-down Sequences Power-up SequencePower-down Sequence Reading the Signature Word and Programming Voltages Slave Programming Mode Device Signature Word and Programming Voltages Slave Programming Circuit and Memory MapDevice Signature Word Programming VCC Location Value Slave Programming Mode Memory Map Operating EnvironmentDescription Address Comments CCR1, CCR0 LOC1 LOC0 IRC1 IRC0 WDE BW1 IRC2Bit Mnemonic Function Slave Programming Routines Address/Command Decoding Routine Program Word Routine Program Word Waveform 10. Dump Word Routine Timing Mnemonics 10. Timing MnemonicsMnemonicDescription Auto Programming Mode Auto Programming Circuit and Memory MapMnemonic Description 12. Auto Programming Circuit Address Internal Address Using Address Internal Address Using Output fromAuto Programming Routine 11 XC196MC/MD Auto Programming Memory Map 13. Auto Programming Routine Auto Programming Procedure Pccb and Uprom Programming 8XC196MH only ROM-dump Mode 14. Pccb and Uprom Programming Circuit RUN-TIME Programming Pins Pccb Programming Uprom Programming13. Pccb and Uprom Programming Values PMODE30 0DH 15. Run-time Programming Code Example Page Instruction Set Reference Page Appendix a Instruction SET Reference Opcode Table A-1. Opcode Map Left Half Table A-1. Opcode Map Right Half Table A-2. Processor Status Word PSW Flags Value of Bits Shifted OffInstruction Quotient Stored Flag Set if Quotient is Table A-4. PSW Flag Setting Symbols Symbol DescriptionInstruction Jumps to Destination if Continues if Variable Description Table A-5. Operand Variables Table A-6. Instruction Set PSW Flag SettingsMnemonic Operation C V VT ST Instruction Format Dest ← Dest and SRCAndb Count PTRS, Cntreg Dstptr ← Srcptr Ptrs ← Srcptr + Count ← Cntreg Loop Srcptr ← Ptrs DstptrCount ← Count Dest Clear BYTE. Clears the value Mnemonic Operation Instruction Format Dest MOD SRC ← Dest MOD SRC Djnzw Decrement and Jump if not Zero Djnz Decrement and Jump if not Zero Epts Enable Peripheral Transaction Dpts Disable Peripheral TransactionEpts EXT SIGN-EXTEND Integer Into Long Extb SIGN-EXTEND SHORT-INTEGER Into Increment BYTE. Increments the value Byte operand by JGE Jump if Signed Greater than or JLE Jump if Signed Less than or Equal Negative flag is set, this instruction adds JNV Jump if Overflow Flag is Clear Jnvt Jump if OVERFLOW-TRAP Flag is JVT Jump if OVERFLOW-TRAP Flag is SET Load Byte SIGN-EXTENDED. Sign Mulb MUL Mulub Mulu SRC, Dest Integer operand Dest ← Dest or SRC Dest ← not Dest PSW/INTMASK ← SP INTMASK1/WSR ← SP SP ← INTMASK1/WSR INTMASK1 ← SP ← PSW/INTMASK PSW/INTMASK ← Scall Wreg, #count SHR Range of 0 to 31 1FH, inclusive. If Shral Arithmetic Right Shift Double Skip Shrl Logical Right Shift DOUBLE-WORD SUB Rightmost operand Subc Subtract Words with Borrow DEST, SRC SubbSubc Subcb Subtract Bytes with Borrow DEST, SRC Index and #MASK = Offset × Offset + Tbase = DestTijmp TBASE, INDEX, #MASK Dest ← Dest XOR SRC XOR Hex Code Instruction Mnemonic Table A-7. Instruction OpcodesClrb Notb Negb Decb Extb Incb Shrb Shlb Shrab Hex Code Hex Code 8XC196MC, MD, MH USER’S Manual EF Lcall Dpts Epts DIV/DIVB/MUL/MULB Note Table A-8. Instruction Lengths and Hexadecimal Opcodes Arithmetic Group Direct Immediate Indirect Indexed MnemonicSubc Subcb Logical Direct Immediate Indirect Opcode Length Stack Direct Immediate Indirect Indexed MnemonicData Direct Jump Direct Call Direct Immediate Indirect Indexed Mnemonic Length OpcodeConditional Jump Direct Immediate Special Mnemonic Direct Immediate Indirect Shift Mnemonic Direct Immediate Indirect IndexedPTS Mnemonic Direct Immediate Indirect Arithmetic Group Indirect Table A-9. Instruction Execution Times in State TimesNormal Autoinc Short Long Reg Mem Mem Reg Mnemonic Direct Immed Normal Autoinc Short Long Reg Mem DIV Divb Divu DivubLogical Stack Register Indirect Normal Autoinc ShortReg Mem LDB Ldbse Ldbze STB XCH Xchb Autoinc Short Long RegAutoinc Short Long Ljmp Sjmp Tijmp Call Memory Indirect Indexed Mnemonic Direct Normal Autoinc Short LongConditional Jump Mnemonic Indirect Indexed Shift Mnemonic DirectClrc Clrvt Idlpd NOP RST Setc SkipPage Signal Descriptions Page Functional Groupings of Signals Signal Name ChangesTable B-1. Signal Name Changes New Name Table B-2 XC196MC Signals Arranged by Functional Categories U8XC196MC Figure B-1 XC196MC 64-lead Shrink DIP Sdip Package X8XC196MC Figure B-2 XC196MC 84-lead Plcc Package Figure B-3 XC196MC 80-lead Shrink EIAJ/QFP Package P7.7/FREQOUT Table B-3 XC196MD Signals Arranged by Functional Categories X8XC196MD Figure B-4 XC196MD 84-lead Plcc Package Figure B-5 XC196MD 80-lead Shrink EIAJ/QFP Package Table B-4 XC196MH Signals Arranged by Functional Categories EA# Extint NMI ONCE# RESET# XTAL1 XTAL2P2.7/SCLK1#/BCLK1 X8XC196MH Figure B-6 XC196MH 64-lead Shrink DIP Sdip Package Figure B-7 XC196MH 84-lead Plcc Package Figure B-8 XC196MH 80-lead Shrink EIAJ/QFP Package Signal Descriptions Table B-6. Signal Descriptions Table B-5. Description of Columns of Table B-6Column Heading Description Name BCLK10 CCR0.1 CCR1.2 BuswidthCOMP1/P2.5/PACT#, COMP2/P2.6/CPVER, COMP3/P2.7MC, MD Command that invoked the power-saving mode System using a clip-on emulator P5.7/BUSWIDTH Slave programming Auto programmingPMODE.30 Programming Start SCLK10# Shift Clock 0 MH only Default Conditions Table B-8 XC196MC and MD Default Signal Conditions Table B-7. Definition of Status SymbolsPort Signals Alternate During Upon RESET# Functions RESET# Active WG2 WK1 NMI WK0 RESET#WG3 WK1 PWM0 WK0 RESET# Table B-9 XC196MH Default Signal ConditionsPort Signals Alternate During Upon Osc output Registers Page Table C-1. Modules and Related Registers CPU8XC196MC, MH, x = Table C-2. Register Name, Address, and Reset Status Xxxx EPA3TIME MC, MD Xxxx EPA2TIME MC, MDXxxx EPA4TIME MD Xxxx EPA5TIME MD Xxxx P1REG MH P7PIN MD1FFD P5REG MC, MD TIMER2 Xxxx TIMER1Usfr MC, MD Usfr MH Xxxx Watchdog Adcommand Adresult Read Adresult Write Adtest Adtime CCR0 ALE CCR1 IRC2 IRC1 IRC0 Comp xCON Address Table C-3 = 0-3 8XC196MC, MH COMPxCON For EPA capture/compare channels 0, 2 Register Address Reset Value Table C-3. COMPxTIME Addresses and Reset ValuesCOMPxTIME Comp xTIME Address EPAxCON = 0-3 8XC196MC x = 0-5 8XC196MD EPAxCON Address Table C-4 = 0-1 8XC196MH = 0-3 8XC196MC = 0-5 8XC196MD Table C-4. EPAxCON Addresses and Reset Values EPA Timer Value Table C-5. EPAxTIME Addresses and Reset ValuesEPAxTIME EPAxTIME = 0-1 8XC196MH x = 0-3 8XC196MC x = 0-5 8XC196MD Freqcnt Freqgen Gencon OVRTM† Intmask INTMASK1 Intpend INTPEND1 Onesreg OnesregFfffh One PxDIR Table C-6. PxDIR Addresses and Reset Values= 1 MH = 2, 5 M PxMODE Table C-7. PxMODE Addresses and Reset Values= 1 MH = 2, 5 Mx PIN7 PIN6 PIN5 PIN4 Pin Special-function Signal Table C-8. Special-function Signals for Ports 1, 2, 5Port 8XC196MC, MD PxPIN Table C-9. PxPIN Addresses and Reset Values PxREG Table C-10. PxREG Addresses and Reset ValuesPxREG = 2-5 8XC196MC = 2-5, 7 8XC196MD x = 1-5 8XC196MH = 2-5 M Pimask Pimask Pipend Pipend PPW150 Ppwvalue PPW PSW PSWPSE PSW Ptssel Ptssrv Pwmcount Pwmperiod PWM xCONTROL Address 1FB0H, 1FB2H PWMxCONTROL SBUFxRX SBUFxRX Address 1F80H, 1F88H = 0-1 8XC196MH8XC196MH Data Received Bit SBUFxTX Sbuf xTX Address 1F82H, 1F8AH = 0-1 8XC196MH8XC196MH Data to Transmit Bit 150 Stack Pointer Stack Pointer SPxBAUD SPxCON Address 1F83H, 1F8BH = 0-1 8XC196MH SPxCON SPxSTATUS T1CONTROL Timer 1 Reload Value T1RELOADT1RELOAD T2CONTROL TIMERx Timer Address 1F7AH1F7EH Usfr Watchdog Watchdog0AH WGCOMPx Wgcontrol Wgcounter Wgoutput Port Wgoutput Waveform Generator Wgoutput Waveform Generator Output Values Output Polarities WG x# Table C-11. Output Configuration Wgprotect Wgreload Byte Windows WSRRegister Mnemonic 00E0-00FFH 00C0-00FFH 00E0-00FFH 00C0-00FFH 0080-00FFH Location 1EH 00FAH TIMER2 † 1F7EH 7BH 00FEH 3DH WGCOMP1 1FC2H T2CONTROL 1F7CH 7BH 00FCH 3DH 1EH TIMER1 † 1F7AH 00FAHPWM0CONTROL 1FB0H 7DH PWM1CONTROL 1FB2H 7DH Zeroreg ZeroregZero Page Glossary Page Glossary Characteristic DOUBLE-WORD LONG-INTEGER LSB Otprom PTS PWM SFR Special interrupt WDT Page Index Page Index Index-2 Index-3 Index-4 Index-5 Index-6 Index-7 Index-8 Index-9 Index-10 Index-11 Index-12 Index-13 Index-14