Intel 8XC196MD, 8XC196MH, 8XC196MC manual 15-18

8XC196MC, MD, MH USER’S MANUAL

After the CCB1 fetch, the internal ready control circuitry allows slow external memory devices to increase the length of the read and write bus cycles. If the external memory device is not ready for access, it pulls the READY signal low and holds it low until it is ready to complete the oper- ation, at which time it releases READY. While READY is low, the bus controller inserts wait states into the bus cycle.

The internal ready control bits, CCR0.5, CCR0.4, and CCR1.1 shown in Figures 15-1 and 15-2, define the maximum number of wait states (0, 1, 2, 3, or infinite) that will be inserted into the bus cycle. While READY is low, wait states are inserted into the bus cycle until the programmed number of wait states is reached. If READY is pulled high before the programmed number of wait states is reached, no additional wait states will be inserted into the bus cycle.

If you choose the infinite wait states option, you must keep P5.6 configured as the READY signal. Also, be sure to add external hardware to count wait states and pull READY high within a spec- ified time. Otherwise, a defective external device could tie up the address/data bus indefinitely.

Setup and hold timings must be met when using the READY signal to insert wait states into a bus cycle (see Figures 15-8 and 15-9, and Table 15-5). Because a decoded, valid address is used to generate the READY signal, the setup time is specified relative to the address being valid. This specification, TAVYV, indicates how much time the external device has to decode the address and assert READY after the address is valid. As shown in Figure 15-9, the 8XC196MH has an addi- tional READY setup timing specification. This specification, TLLYV, indicates how much time an external device has to deassert the READY signal after ALE falls.

The READY signal must be held low until the minimum TCLYX timing specification is met. Do not exceed the maximum TCLYX or TLLYX specification or additional (unwanted) wait states might be added. Refer to the datasheets for the current TAVYV , TCLYX, and TLLYX specifications.

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