8XC196MC, MD, MH USER’S MANUAL
5-6
5.3.1 Special Interrupts
This microcontroller has three special interrupt sources that are always enabled: unimplemented
opcode, software trap, and NM I. The se int errupts a re not affecte d by t he EI (enable inte rrupts)
and DI (disable interrupts) instructions, and they cannot be masked. All of these inte rrupts are
serviced by the interrupt controller; they cannot be assigned t o the PTS. Of these three, only NMI
goes through the transition detector and priority encoder. The other two special interrupts go di-
rectly to the interrupt controller for servic ing. Be aware that these interrupts are often assigned to
special functions in development tools.
5.3.1.1 Unimplemented Opcode
If the CPU attempts to execute an unimplemented opcode, an indirect vector through location
2012H occurs. This prevents random software execution during hardware and software failures.
The interrupt vector should contain the starting address of an error routine that will not further
corrupt an already erroneous situation. The unimplemented opcode i nterrupt prevents other int er-
rupt requests from being acknowledged until after the next instruction is executed.
5.3.1.2 Software Trap
The TRAP instruction (opcode F7H) causes an int errupt call that is vectored through locati on
2010H. The TRAP instruction provides a single-instruc tio n inter r upt that is useful when debug-
ging software or generating software interrupts. The TRAP instruction prevents ot her interrupt
requests from being acknowledged until after the next instruct ion is exec ute d.
5.3.1.3 NMI
The external NMI pin generates a nonmaskable interrupt for implementation of critical inter r upt
routines. NMI has the highest priority of all the prioritized inte rrupts. It is passe d directly fr om
the transition detector to the priority encoder, and it vectors indirectly through location 203EH.
The NMI pin is sampled during phase 2 (CLKOUT high) and is latched internally. Because inter-
rupts are edge-triggered, only one interrupt is generated, even if the pin is hel d high.
If your system does not use the NMI interrupt, connect the NMI pin to VSS to prevent spurious
interrupts.
5.3.2 External Interrupt Pin
The protection circuitry in the waveform generator ( Figure 5-2) m onitors the external interr upt
(EXTINT) signal. When it detects a valid event on the input, it sumultaneously disa bles the wave-
form generator outputs and generates an EXTINT interrupt request. Bits 2 and 3 in the waveform
generator protection (WG_PROTECT) register (Figure 9-9 on page 9-15) select the type of ex-
ternal event that will generate an int errupt request: a falling or rising edge or a low or hi gh level.