Intel 8XC196MH, 8XC196MD, 8XC196MC manual Index-3

Clock

external, 13-7

generator, 2-7, 13-7, 13-8 internal, and idle mode, 14-4, 14-5 phases, internal, 2-8

CLR instruction, A-2, A-10, A-41, A-47, A-52 CLRB instruction, A-2, A-11, A-41, A-47, A-52 CLRC instruction, A-3, A-11, A-46, A-51, A-57 CLRVT instruction, A-3, A-11, A-46, A-51, A-57 CMP instruction, A-3, A-11, A-43, A-47, A-52 CMPB instruction, A-3, A-11, A-44, A-47, A-52 CMPL instruction, A-2, A-12, A-45, A-47, A-52 Code execution, 2-5, 2-6

COMP0_TIME, C-68

COMP1_CON, C-68

COMP1_TIME, C-68

COMP5:0, 11-3, B-15 CompuServe forums, 1-10 Conditional jump instructions, A-5 Configuring external memory pins, 15-5 CPU, 2-4

CPVER, 16-12, B-15 Customer service, 1-8

D

D/A converter, 10-10

Data instructions, A-49, A-55 Data types, 3-1–3-4

addressing restrictions, 3-1 converting between, 3-4 defined, 3-1

iC-96, 3-1 PLM-96, 3-1

signed and unsigned, 3-1, 3-4 values permitted, 3-1

Datasheets online, 1-10 ordering, 1-7

Deassert, defined, 1-3

DEC instruction, A-2, A-12, A-41, A-47, A-52 DECB instruction, A-2, A-12, A-41, A-47, A-52 DED bit, 16-6–16-7, 16-30

DEI bit, 16-6–16-7, 16-17 Design considerations

waveform generator, 9-19, 9-20 Device

minimum hardware configuration, 13-1

INDEX

pin reset status, B-23, B-25 programming, 16-1–16-33

reset, 13-8, 13-9, 13-10, 13-11, 13-12 DI instruction, A-3, A-12, A-46, A-51, A-57 Digital-to-analog converter, 10-10

DIR bit, 7-2, 7-6

Direct addressing, 3-6, 3-9

DIV instruction, A-13, A-46, A-48, A-53 DIVB instruction, A-13, A-46, A-48, A-53 DIVU instruction, A-3, A-13, A-43, A-48, A-53 DIVUB instruction, A-3, A-14, A-44, A-48, A-53 DJNZ instruction, A-2, A-5, A-14, A-45, A-50,

A-56

DJNZW instruction, A-2, A-5, A-14, A-45, A-50, A-56

Documents, related, 1-5–1-8 DOUBLE-WORD, defined, 3-3

DPTS instruction, A-3, A-15, A-45, A-51, A-57 Dump-word routine, 16-24

E

EA#, 16-13, B-15 and P5.0, 6-13 and P5.3, 6-13

and programming modes, 16-14

idle, powerdown, reset status, B-24, B-25

EEopcode, and unimplemented opcode interrupt, A-3, A-46

EI instruction, 5-13, A-3, A-15, A-46, A-51, A-57 EPA, 2-10, 11-1–11-24

and PTS, 11-12 block diagram, 11-2 capture data overruns, 11-21 capture/compare channels

programming, 11-18

choosing capture or compare mode, 11-19 clock prescaler, 11-16, 11-17

compare channels programming, 11-18

compare modules programming, 11-18

controlling the clock source and direction, 11-16, 11-17

determining event status, 11-24 enabling a timer/counter, 11-16, 11-17 enabling the compare function, 11-22 overruns, 11-12, 11-13

Index-3