Intel 8XC196MC, 8XC196MD, 8XC196MH manual Pipend

8XC196MC, MD, MH USER’S MANUAL

PI_PEND

PI_PEND (Continued)	Address:	1FBEH
	Reset State:	AAH

When hardware detects a pending peripheral or timer interrupt, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers and the peripheral interrupt pending (PI_PEND) register. When the vector is taken, the hardware clears the INT_PEND/INT_PEND1 pending bit. Reading this register clears all the PI_PEND bits. Software can generate an interrupt by setting a PI_PEND bit.

	7
8XC196MC	—	—	—	WG
	7
8XC196MD	—	COMP5	—	WG
	7
8XC196MH	—	SP1	—	SP0

			0
—	OVRTM2	—	OVRTM1
			0
—	OVRTM2	—	OVRTM1
			0
—	OVRTM2	—	OVRTM1

Bit	Bit	Function
Number	Mnemonic
0	OVRTM1	Timer 1 Overflow/Underflow
		When set, this bit indicates a pending timer 1 overflow/underflow interrupt.
		The timer 1 and timer 2 overflow/underflow interrupts are associated with
		the overflow/underflow timer interrupt (OVRTM). Setting INT_MASK.0
		enables OVRTM. Setting PI_MASK.0 enables OVRTM1.

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