Intel 8XC196MD Bidirectional Port Operation, Bidirectional Port Control and Status Registers

8XC196MC, MD, MH USER’S MANUAL

Table 6-5 lists the registers associated with the bidirectional ports. Each port has three control reg- isters (Px_MODE, Px_DIR, and Px_REG); they can be both read and written. The Px_PIN regis- ter is a status register that returns the logic level present on the pins; it can only be read. The registers for the standard ports are byte-addressable and can be windowed. The port 5 registers must be accessed using 16-bit addressing and cannot be windowed. “Bidirectional Port Consid- erations” on page 6-12 discusses special considerations for reading P2_REG.7 and P6_REG.7:4.

Table 6-5. Bidirectional Port Control and Status Registers

Mnemonic	Address		Description
P1_DIR (MH)	1F9BH	Port x Direction
P2_DIR	1FD2H	Each bit of Px_DIR controls the direction of the corresponding pin.
P5_DIR	1FF3H
		0 = complementary output (output only)
P7_DIR (MD)	1FD3H
		1 =	input or open-drain output (input, output, or bidirectional) Open-
			drain outputs require external pull-ups.
P1_MODE (MH)	1F99H	Port x Mode
P2_MODE	1FD0H	Each bit of Px_MODE controls whether the corresponding pin
P5_MODE	1FF1H
		functions as a standard I/O port pin or as a special-function signal.
P7_MODE (MD)	1FD1H
		0 =	standard I/O port pin
		1 =	special-function signal
P1_PIN (MH)	1F9FH	Port x Input
P2_PIN	1FD6H	Each bit of Px_PIN reflects the current state of the corresponding
P5_PIN	1FF7H
		pin, regardless of the pin configuration.
P7_PIN (MD)	1FD7H
P1_REG (MH)	1F9DH	Port x Data Output
P2_REG	1FD4H	For an input, set the corresponding Px_REG bit.
P5_REG	1FF5H
		For an output, write the data to be driven out by each pin to the
P7_REG (MD)	1FD5H
		corresponding bit of Px_REG. When a pin is configured as standard
		I/O (Px_MODE.y = 0), the result of a CPU write to Px_REG is
		immediately visible on the pin. When a pin is configured as a
		special-function signal (Px_MODE.y = 1), the associated on-chip
		peripheral or off-chip component controls the pin. The CPU can still
		write to Px_REG, but the pin is unaffected until it is switched back to
		its standard I/O function.
		This feature allows software to configure a pin as standard I/O (clear
		Px_MODE.y), initialize or overwrite the pin value, then configure the
		pin as a special-function signal (set Px_MODE.y). In this way, initial-
		ization, fault recovery, exception handling, etc., can be done without
		changing the operation of the associated peripheral.

6.3.1Bidirectional Port Operation

Figure 6-2 shows the logic for driving the output transistors, Q1 and Q2. Q1 can source at least –3 mA at V CC – 0.7 volts. Q2 can sink at least 3 mA at 0.45 volts. (Consult the datasheet for spec- ifications.)

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