SPxCON Address 1F83H, 1F8BH = 0-1 8XC196MH | Intel 8XC196MD specs

		REGISTERS
		SPx_CON

SPx_CON	Address:	1F83H, 1F8BH
x = 0–1 (8XC196MH)	Reset State:	00H

The serial port control (SPx_CON) register selects the communications mode and enables or disables the receiver, parity checking, and nine-bit data transmission.

8XC196MH

7

M2	DIR	PAR	TB8

0

REN	PEN	M1	M0

	Bit	Bit				Function
	Number	Mnemonic				Function
	Number	Mnemonic

	7	M2	See description for bits 0 and 1.

	6	DIR	Synchronous Clock Direction
			This bit determines the direction of the clock during synchronous mode.
			0 = output
			1 = input

	5	PAR	Parity Selection Bit
			This bit selects even or odd parity.
			0 = even parity
			1 = odd parity

	4	TB8	Transmit Ninth Data Bit
			This is the ninth data bit that will be transmitted in mode 2 or 3. This bit is
			cleared after each transmission, so it must be set before SBUFx_TX is
			written. When parity is enabled (SPx_CON.2 = 1), this bit takes on the
			even parity value.

	3	REN	Receive Enable
			Setting this bit enables receptions. When this bit is set, a falling edge on
			the RXDx pin starts a reception in mode 1, 2, or 3. In mode 0, this bit must
			be clear for transmission to begin and must be set for reception to begin.
			Clearing this bit stops a reception in progress and inhibits further
			receptions. To avoid a partial or undesired reception, clear this bit before
			clearing the RI flag in SPx_STATUS. This can be handled in an interrupt
			environment by using software flags or in straight-line code by using the
			interrupt pending register to signal the completion of a reception.

	2	PEN	Parity Enable
			In modes 1 and 3, setting this bit enables the parity function. This bit must
			be cleared if mode 2 is used. When this bit is set, TB8 takes the parity
			value on transmissions and SPx_STATUS.7 becomes the receive parity
			error bit.

	1:0	M1:0	Mode Selection
			These bits along with bit 7 select the communications mode.
			M2	M1	M0
			0	0	0	synchronous mode 0
			X	0	1	mode 1
			X	1	0	mode 2
			X	1	1	mode 3
			1	0	0	synchronous mode 4

C-51

Image 528

Intel 8XC196MD, 8XC196MC manual SPxCON Address 1F83H, 1F8BH = 0-1 8XC196MH

Contents

8XC196MC, 8XC196MD, 8XC196MH Microcontroller User’ Manual We Value Your Opinion Page 8XC196MC, 8XC196MD, 8XC196MH Microcontroller User’s Manual Intel Corporation Contents Chapter Memory Partitions Contents 8XC196MC, MD, MH USER’S Manual PWM Signals and Registers Functional Overview Programming the Frequency GeneratorApplication Example Programming the Waveform Generator Chapter Event Processor Array EPA Chapter Minimum Hardware Considerations Chapter Programming the Nonvolatile Memory Appendix C Registers Glossary Index Figures 10-5 15-9 Ready Timing Diagram One Wait State 8XC196MH 15-21 Tables 11-12 16-7 Pmode Values Guide to This Manual Page Manual Contents Chapter Guide to this Manual Special Operating Modes Notational Conventions and Terminology Assert and deassert Numbers Related Documents Handbooks and Product Information Application Notes, Application Briefs, and Article ReprintsTitle Order Number MCS 96 Microcontroller Datasheets Commercial/Express MCS 96 Microcontroller Datasheets Automotive This Page Left Intentionally Blank Guide to this Manual This Page Left Intentionally Blank World Wide Web Technical SupportProduct Literature Page Architectural Overview Page Microcontroller Features Typical Applications Features of the 8XC196Mx Product Family Functional OverviewOtprom SIO PWM ROM PTS EPA PWM WDT SIOCPU RAM CPU Control Register FileRegister Arithmetic-logic Unit Ralu Code Execution Instruction Format Interrupt Service Memory Interface Unit Internal Timing Clock Circuitry Internal Peripherals State Times at Various Frequencies 1 I/O Ports Serial I/O SIO Port Event Processor Array EPA and Timer/Counters Pulse-width Modulator PWMFrequency Generator Waveform Generator Watchdog Timer Reducing Power ConsumptionTesting the Printed Circuit Board Analog-to-digital Converter Programming the Nonvolatile Memory Programming Considerations Page Overview of the Instruction SET Operand Type DefinitionsOperand Type No. Signed Possible Values Addressing Restrictions BIT Operands Byte OperandsSHORT-INTEGER Operands Word Operands Integer Operands DOUBLE-WORD Operands LONG-INTEGER Operands Converting OperandsConditional Jumps Floating Point Operations Addressing Modes Direct Addressing Immediate AddressingIndirect Addressing Definition of Temporary Registers Indexed Addressing Indirect Addressing with AutoincrementIndirect Addressing with the Stack Pointer Short-indexed Addressing Long-indexed Addressing Zero-indexed Addressing Assembly Language Addressing Mode Selections Using RegistersSoftware Standards and Conventions Addressing 32-bit Operands Linking Subroutines Software Protection Features and Guidelines 8XC196MC, MD, MH USER’S Manual Memory Partitions Page Memory Partitions External Devices Memory or I/OProgram and Special-purpose Memory Program Memory Memory MapDevice Description Addressing Modes Special-purpose Memory Special-purpose Memory AddressesReserved Memory Locations Interrupt and PTS Vectors Chip Configuration Bytes CCBs Special-function Registers SFRsSecurity Key Memory-mapped SFRs Peripheral SFRs EPA and Timer SFRs Peripheral SFRs 8XC196MCPort 2 SFRs SFRs Peripheral SFRs 8XC196MD Ports 2 and 7 SFRs Peripheral SFRs 8XC196MH Port 0 and 2 SFRsPort 1 SFRs Serial I/O Port SFRs Register File Memory Map Address Register File Memory Addresses General-purpose Register RAMStack Pointer SP Device and Hex Address Range Description Addressing Modes CPU Special-function Registers SFRs CPU SFRsAddress High Odd Byte Low Even Byte Windowing 8XC196MC,MD02FFH 01FFH 00FFH Selecting a Window WSRBit Function Number WSR Value for Peripherals Addressing a Location Through a Window 10. Selecting a Window of the Upper Register File 11. Windows 12. Windowed Base AddressesBase WSR Value WSR Value for Peripheral SFRs 2.1 32-byte Windowing Example 2.2 64-byte Windowing Example2.3 128-byte Windowing Example Unsupported Locations Windowing Example Using the Linker Locator to Set Up a Window ?WSR This listing shows the disassembled code Windowing and Addressing Modes LDB WSR, #12HPage Standard and PTS Interrupts Page Chapter Standard and PTS Interrupts Overview of Interrupts Flow Diagram for PTS and Standard Interrupts Interrupt Signals and Registers Interrupt SignalsInterrupt and PTS Control and Status Registers Interrupt Sources and Priorities Pipend 1FBEHPtssel Ptssrv Interrupt Controller PTS Service Interrupt Sources, Vectors, and PrioritiesInterrupt Source Mnemonic Name Vector Priority Special Interrupts External Interrupt PinUnimplemented Opcode Software Trap Multiplexed Interrupt Sources Waveform Generator Protection Circuitry Flow Diagram for the Ovrtm Interrupt End-of-PTS Interrupts Interrupt LatencySituations that Increase Interrupt Latency Calculating Latency Standard Interrupt Latency Standard Interrupt Response Time PTS Interrupt Latency PTS Mode Execution Time in State Times Programming the InterruptsExecution Times for PTS Cycles Standard and PTS Interrupts Ptssel 8XC196MC8XC196MD Bit Function Intmask COMP2 EPA2 COMP1 EPA1 COMP3 COMP0 EPA0 OvrtmBit Mnemonic Interrupt Standard Vector COMP2 MC, MD INTMASK1 NMI ExtintNMI Extint EPA5 NMI Extint SPI COMP3 EPA3 COMP4 EPA4 RI1 RI0 TI1 TI0 Pimask 8XC196MC 8XC196MDBit Function Number Mnemonic Modifying Interrupt Priorities PimaskOVRTM1 Standard and PTS Interrupts Determining the Source of an Interrupt 10. Interrupt Pending Intpend Register Intpend 11. Interrupt Pending 1 INTPEND1 Register INTPEND1 12. Peripheral Interrupt Pending Pipend Register Pipend Initializing the PTS Control Blocks Pipend Specifying the PTS Count 14. PTS Service Ptssrv Register Ptssrv Selecting the PTS Mode Single Transfer ModePtscon PTS Single Transfer Mode Control Block Ptsdst H Ptsdst L Ptssrc H Ptssrc L Ptscon PtscountRegister Location Function Ptsdst Ptscb + Standard and PTS Interrupts Block Transfer Mode Single Transfer Mode PtscbBlock Transfer Mode Ptscb PTS Block Transfer Mode Control Block Ptsblock Ptscb + 5 A/D Scan Mode PTS A/D Scan Mode Control Block A/D Scan Mode Command/Data Table Address Contents 5.1 A/D Scan Mode Cycles 5.2 A/D Scan Mode Example Command/Data Table Example A/D Scan Mode Ptscb ExamplePTSPTR2 H = 1FH PTSPTR2 L = AAH Ptscount = 04H 5.3 A/D Scan Mode Example 10. Command/Data Table Example11. A/D Scan Mode Ptscb Example Serial I/O Modes PTS Serial I/O Mode Control Block 1 8XC196MC, MD SA1 SA0 MAJPtsvec Baud EparegSA1 SA0 † 8XC196MC, MD, MH USER’S Manual PTS Serial I/O Mode Control Block 2 8XC196MC, MD Port Mask RegisterPort Address Pointer high byte Data PTSCON1Rpar PTS Serial I/O Mode Control Block 8XC196MC, MD Register Location FunctionPortreg 8XC196MC, MD, MH USER’S Manual 13. Ssio Transmit Mode PTSCBs PTSCB1 PTSCB2 Txddone = Synchronous SIO Receive Mode Example 23. Synchronous SIO Receive Timing 14. Ssio Receive Mode PTSCBs Clrb Rxddone Standard and PTS Interrupts Rxddone = 25. Asynchronous SIO Transmit Timing 15. Asio Transmit Mode PTSCBs Standard and PTS Interrupts End-Of-PTS Interrupt Save Critical Data Is PTS Asynchronous SIO Receive Mode Example 27. Asynchronous SIO Receive Timing 16. Asio Receive Mode PTSCBs Samptime = 01HPortreg H = 1FH P2PIN Standard and PTS Interrupts End-Of-PTS Interrupt Ports Page I/O Ports Overview Device I/O PortsPort Bits Type Direction Associated Peripherals Standard Input-only Port Pins INPUT-ONLY Ports 1 MC, MD only Standard Input-only Port Operation Input-only Port Registers1FDAH MH P1PIN MC, MD Standard Input-only Port Considerations Bidirectional Ports 1 MH ONLY, 2, 5, and 7 MD only Bidirectional Port Pins Port Pin Special-function Associated Signals Bidirectional Port Operation Bidirectional Port Control and Status Registers Ports Bidirectional Port Structure Bidirectional Port Pin Configurations Logic Table for Bidirectional Ports in I/O ModeSfdir 8XC196MC, MD, MH USER’S Manual Bidirectional Port Pin Configuration Example Control Register Values for Each ConfigurationPort Configuration Example Bidirectional Port Considerations HZ1 P5.1/INST Ports 3 and 4 Pins Port Pins Special-functionBidirectional Ports 3 and 4 ADDRESS/DATA BUS 12. Ports 3 and 4 Control and Status Registers Bidirectional Ports 3 and 4 Address/Data Bus Operation Address/Data Bus Ports 3 and 4 Structure Using Ports 3 and 4 as I/O Design Considerations for Ports 3Standard OUTPUT-ONLY Port 13. Logic Table for Ports 3 and 4 as Open-drain I/O Configuring Output-only Port Pins 14. Standard Output-only Port PinsOutput-only Port Operation 15. Output-only Port Control Register Reset State 0000H Wgoutput Port Address1FC0H OP1 OP0 Reset State 0000H Wgoutput PortPage Serial I/O SIO Port Page SIO Block Diagram Serial I/O SIO Port Functional Overview Serial I/O Port Signals and Registers Serial Port SignalsSerial Port Control and Status Registers P1DIR 1F9BH P1PIN 1F9FHP1REG 1F9DH Serial Port Modes Synchronous Modes Modes 0 Mode Mode 0 Timing Asynchronous Modes Modes 1, 2, Serial Port Frames for Mode Mode 2 and 3 Timings Multiprocessor Communications Configuring the Serial Port Pins Programming the Serial PortProgramming the Control Register SP xCON Address 1F83H, 1F8BH = 0-1 8XC196MH Bit Function Programming the Baud Rate and Clock Source ClksrcBV7 BV9 BV8 Baudvalue = Bclk SPxBAUD Values When Using XTAL1 at 16 MHz Enabling the Serial Port Interrupts80CFH E82BH Determining Serial Port Status RPE/RB8 TXERPE/RB8 8XC196MC, MD, MH USER’S Manual Frequency Generator Page Chapter Frequency Generator Frequency Generator Signal Frequency Generator Control and Status RegistersPort Frequency Configuring the Output Programming the Frequency GeneratorProgramming the Frequency Freqgen Determining the Current Value of the Down-counter Application ExampleFreqcnt Frequency Generator 0FAH Xmitbuf Dsb Bufsize Block of data to send Shiftreg Stb temp,freqgen0 Into freq gen Frequency Generator Page Waveform Generator Page Chapter Waveform Generator Waveform Generator Functional Overview Waveform Generator Block Diagram Waveform Generator Signals and Registers Waveform Generator SignalsWaveform Generator Control and Status Registers Waveform Generator Operation Timebase Generator Phase Driver Channels Control and Protection Circuitry Register Buffering and Synchronization Protection Circuitry Operating Modes Register Updates Event ModeOperation in Center-aligned and Edge-aligned Modes Step Center-aligned Modes Edge-aligned Modes Center-aligned Modes Center-aligned Modes Counter Operation Center-aligned Modes Output Operation Edge-Aligned Modes Edge-aligned Modes Counter Operation Configuring the Outputs Output ConfigurationProgramming the Waveform Generator Wgoutput Waveform Generator OP1 OP0 Sync PE7PE6 OP1 8XC196MC, MD, MH USER’S Manual Wgprotect F0HE0H 8XC196MC, MD 8XC196MH Bit Function Number Mnemonic Specifying the Carrier Period and Duty Cycle WgreloadReload 150 Reload Wgcomp Address 1FC2H,1FC4H,1FC6H Wgcontrol DT7 DT6 DT5 DT4 DT9 DT8 DT3 DT2 DT1 DT0Wgcounter = Wgreload Determining the Waveform GENERATOR’S Status Enabling the Waveform Generator InterruptsWgcounter Xxxxh Design Considerations Dead Time and Duty CycleWgcount WGCOUNT= Wgcomp Programming Example Ph3 Dsw P6.4,5 config Waveform Generator Temp1,WGOUTPUT0 Now store it Ret Demo board PI interrupt Page Pulse-width Modulator Page Chapter PULSE-WIDTH Modulator PWM Functional Overview PWM Signals and Registers PWM Signals PWM Operation PWM Control and Status RegistersPEx Pin Output Programming the Frequency and Period E6HFFH PWM Output Frequencies Fpwm Pwmperiod Programming the Duty Cycle Pwmperiod + Sample Calculations Reading the Current Value of the Down-counterPWM xCONTROL Address 10-3 PWM Output Alternate Port Function PWM Output Enabled When Enabling the PWM OutputsPWM Output Alternate Functions Pwmcount Waveform Generator Output Configuration Wgoutput Register D/A Buffer Block Diagram Generating Analog Outputs Event Processor Array EPA Page EPA Functional Overview EPA ChannelsDevice Capture/Compare Channels Compare-only Channels COMP30 EPA and TIMER/COUNTER Signals and Registers EPA and Timer/Counter Signals EPA Control and Status Registers P0PIN 1FA8H P1PIN 1FA9H TIMER/COUNTER Functional Overview TIMER1 1F7AHTIMER2 1F7EH T1RELOAD EPA Timer/Counters Cascade Mode Timer 2 Only Quadrature Clocking Modes State of Xinternal State of Yinternal Count Direction T1DIR Quadrature Mode Timing and Count EPA Channel Functional Overview Operating in Capture Mode A Single EPA Capture/Compare Channel EPA Simplified Input-capture Structure Action Taken When a Valid Edge Occurs Overwrite Bit Status Action Taken When a Valid Edge OccursEPA Overruns EPAxCON.0 Operating in Compare Mode Preventing EPA OverrunsGenerating a Low-speed PWM Output Generating the Highest-speed PWM Output Programming the EPA and TIMER/COUNTERS Configuring the EPA and Timer/Counter SignalsProgramming the Timers Prescaler Divisor Resolution † T1CONTROLClock Source Direction Source Prescaler Resolution † T2CONTROL Example EPA Control Register Settings for Channels 1, 3, or Mode WGR ROT ON/RTProgramming the Capture/Compare Channels Capture Mode Event Compare Mode ActionEPAxCON = 0-1 8XC196MH x = 0-3 8XC196MC x = 0-5 8XC196MD = 0, 2 = 1, 3 EPA xCON Address = 0, 2For EPA capture/compare channels 0, 2 For EPA capture/compare channels 1, 3 Capture Mode on Compare Mode RT = 0-3 8XC196MC, MH = 0-5 8XC196MD Reset State 00H Programming the Compare-only ChannelsComp xCON Address WGR ROT Enabling the EPA Interrupts Determining Event Status Analog-to-digital Converter PageNum-38 12.1 A/D Converter Functional Overview Angnd 12.2 A/D Converter Signals and Registers A/D Converter PinsPort Pin Signal Description A/D Control and Status Registers 12.3 A/D Converter Operation P1PIN MC,MD Programming the A/D Converter Programming the A/D Test Register AdtestOFF1 OFF0 Programming the A/D Time Register Adresult Write Programming the A/D Command Register Adtime Adcommand M1 M0 ModeEnabling the A/D Interrupt ACH3 ACH2 ACH1 ACH0 Determining A/D Status and Conversion Results Adresult ReadADRLT90 Designing External Interface Circuitry Idealized A/D Sampling Circuitry Minimizing the Effect of High Input Source Resistance Suggested A/D Input Circuit Understanding A/D Conversion Errors Using Mixed Analog and Digital Inputs 12-14 Ideal A/D Conversion Characteristic 10. Actual and Ideal A/D Conversion Characteristics 12-17 11. Terminal-based A/D Conversion Characteristic Minimum Hardware Considerations Page Minimum Required Signals RESET#Minimum Connections I/O Port Configuration Guide Port Where to Find Configuration InformationUnused Inputs 13.1.2 I/O Port Pin Connections Minimum Hardware Connections Applying and Removing Power Noise Protection Tips ON-CHIP Oscillator Circuitry On-chip Oscillator Circuit External Crystal Connections Using AN External Clock Source External Clock Connections Resetting the Device Reset Timing Sequence Gencon Rsts DR0Rsts DRO Generating an External Reset Internal Reset Circuitry 10. Minimum Reset Circuit Issuing the Reset RST Instruction Enabling the Watchdog TimerIssuing an Illegal Idlpd Key Operand Generating Wait States Selecting the Watchdog Reset Interval 8XC196MH only First Byte Second Byte Reset Interval1EH E1H 1EH A1HPage Special Operating Modes Page Special Operating Mode Signals and Registers Operating Mode Control SignalsPort Pin Signal Type Description Clkout Operating Mode Control and Status Registers Port Pin Signal Type Description NameONCE# CCR0 Reducing Power Consumption P1MODEMHP7MODEMD 1FD1H P1REG MH 1F9DH Idle Mode Clock Control During Power-saving Modes Powerdown Mode Enabling and Disabling Powerdown Mode Entering Powerdown Mode Exiting Powerdown ModeGenerating a Hardware Reset Driving the VPP Pin Low Asserting the External Interrupt Signal External RC Circuit Selecting R1 and C1 Typical Voltage on the VPP Pin While Exiting Powerdown Once Mode Reserved Test Modes Page Interfacing with External Memory Page External Memory Interface Signals and Registers External Memory Interface SignalsSignal Port Pin Type Description Name ADV# Bytes Accessed BHE# AD0CCR0.1 CCR1.2 Buswidth Signal Port Pin EA#WR# External Memory Interface Registers WRH#WRL# Register Address Description Mnemonic Chip Configuration Registers and Chip Configuration Bytes P5REG = 11XX XxxxbBHE#/WRH# † 15-6 CCR0 LOC1 LOC0 IRC1 IRC0 ALE BW0LOC1 LOC0 IRC2 IRC1 IRC0 CCR0 ALEBW1 BW0 CCR1 WDE BW1 IRC2WDE BUS Width and Multiplexing CCR1 Multiplexing and Bus Width Options Buswidth Timing Diagram 8XC196MC, MD Buswidth Signal Timing Definitions Symbol DefinitionTiming Requirements for Buswidth 15.3.2 16-bit Bus Timings Timings for 16-bit Buses 15.3.3 8-bit Bus Timings Wait States Ready Control Timings for 8-bit Buses 15-18 Ready Timing Diagram One Wait State 8XC196MC, MD Address Valid to Ready Setup Bus-control Mode Bus-control Signals CCR0.3 CCR0.2 BUS-CONTROL ModesBus-control Modes Standard Bus-control Mode BHE# WR# AD0 CS# ALE OE# WE# RD# WR# Buswidth CS# Eprom RAMOE# WE# RD# WR# Write Strobe Mode 14. Write Strobe Mode 15 -bit System with Writes to Byte-wide RAMs OE# OE# WE# RD# WRH# WRL# Address Valid Strobe Mode 16. Address Valid Strobe Mode 18 -bit System with Flash Eprom OE# RD# Address Valid with Write Strobe Mode 20. Timings of Address Valid with Write Strobe Mode System BUS AC Timing Specifications VCC BuswidthWRH# WRL# CS# WE# CS# 22. System Bus Timing Explanation of AC Symbols AC Timing Symbol Definitions SignalsExternal Memory Systems Must Meet These Specifications AC Timing Definitions Microcontroller Meets These Specifications Address Setup to ALE/ADV# Low 15-35 Page Programming Nonvolatile Memory Page Programming the Nonvolatile Memory Programming Methods Otprom Memory MAP Security Features Controlling Access to Internal MemoryC196Mx Otprom Memory Map Address Range Description Hex Controlling Access to the Otprom During Normal Operation Memory Protection for Normal Operating ModeControlling Access to the Otprom During Programming Modes Read Protect Write Protect Protection Status Memory Protection Options for Programming Modes Security KeyPccb CCB Controlling Fetches from External Memory Uprom Programming Values and Locations for Slave Mode UsfrTo set this bit Write this value To this location Programming Pulse Width PpwvaluePPW BitBitFunction Number Mnemonic Modified QUICK-PULSE Algorithm Example Ppwvalue Calculations8XC196MC, MD 8XC196MH Two 250-µs pulses required Ppwvalue = Modified Quick-pulse Algorithm Programming Mode Pins Special Program Port Pin PROG# AINC#Cpver PACT# Selecting the Programming Mode Entering Programming ModesPmode Values Power-up and Power-down Sequences Power-up SequencePower-down Sequence Slave Programming Mode Reading the Signature Word and Programming Voltages Slave Programming Circuit and Memory Map Device Signature Word and Programming VoltagesDevice Signature Word Programming VCC Location Value Slave Programming Mode Memory Map Operating EnvironmentDescription Address Comments CCR1, CCR0 LOC1 LOC0 IRC1 IRC0 WDE BW1 IRC2Bit Mnemonic Function Slave Programming Routines Address/Command Decoding Routine Program Word Routine Program Word Waveform 10. Dump Word Routine Timing Mnemonics 10. Timing MnemonicsMnemonicDescription Auto Programming Mode Auto Programming Circuit and Memory MapMnemonic Description 12. Auto Programming Circuit Address Internal Address Using Output from Address Internal Address UsingAuto Programming Routine 11 XC196MC/MD Auto Programming Memory Map 13. Auto Programming Routine Auto Programming Procedure ROM-dump Mode Pccb and Uprom Programming 8XC196MH only 14. Pccb and Uprom Programming Circuit Pins Pccb Programming Uprom Programming RUN-TIME Programming13. Pccb and Uprom Programming Values PMODE30 0DH 15. Run-time Programming Code Example Page Instruction Set Reference Page Appendix a Instruction SET Reference Table A-1. Opcode Map Left Half Opcode Table A-1. Opcode Map Right Half Table A-2. Processor Status Word PSW Flags Value of Bits Shifted OffInstruction Quotient Stored Flag Set if Quotient is Table A-4. PSW Flag Setting Symbols Symbol DescriptionInstruction Jumps to Destination if Continues if Table A-5. Operand Variables Variable Description PSW Flag Settings Table A-6. Instruction SetMnemonic Operation C V VT ST Instruction Format Dest ← Dest and SRCAndb PTRS, Cntreg Count Count ← Cntreg Loop Srcptr ← Ptrs Dstptr Dstptr ← Srcptr Ptrs ← Srcptr +Count ← Count Dest Clear BYTE. Clears the value Mnemonic Operation Instruction Format ← Dest MOD SRC Dest MOD SRC Djnz Decrement and Jump if not Zero Djnzw Decrement and Jump if not Zero Dpts Disable Peripheral Transaction Epts Enable Peripheral TransactionEpts EXT SIGN-EXTEND Integer Into Long Extb SIGN-EXTEND SHORT-INTEGER Into Increment BYTE. Increments the value Byte operand by JGE Jump if Signed Greater than or JLE Jump if Signed Less than or Equal Negative flag is set, this instruction adds JNV Jump if Overflow Flag is Clear Jnvt Jump if OVERFLOW-TRAP Flag is JVT Jump if OVERFLOW-TRAP Flag is SET Load Byte SIGN-EXTENDED. Sign MUL Mulb Mulu Mulub Integer operand SRC, Dest Dest ← not Dest Dest ← Dest or SRC INTMASK1/WSR ← SP PSW/INTMASK ← SP SP ← PSW/INTMASK PSW/INTMASK ← SP ← INTMASK1/WSR INTMASK1 ← Scall Wreg, #count SHR Range of 0 to 31 1FH, inclusive. If Shral Arithmetic Right Shift Double Shrl Logical Right Shift DOUBLE-WORD Skip Rightmost operand SUB Subb Subc Subtract Words with Borrow DEST, SRCSubc Subcb Subtract Bytes with Borrow DEST, SRC Index and #MASK = Offset × Offset + Tbase = DestTijmp TBASE, INDEX, #MASK XOR Dest ← Dest XOR SRC Table A-7. Instruction Opcodes Hex Code Instruction MnemonicClrb Notb Negb Decb Extb Incb Shrb Shlb Shrab Hex Code Hex Code 8XC196MC, MD, MH USER’S Manual Dpts Epts EF Lcall DIV/DIVB/MUL/MULB Note Table A-8. Instruction Lengths and Hexadecimal Opcodes Arithmetic Group Direct Immediate Indirect Indexed MnemonicSubc Subcb Logical Direct Immediate Indirect Stack Direct Immediate Indirect Indexed Mnemonic Opcode LengthData Direct Jump Direct Call Direct Immediate Indirect Indexed Mnemonic Length OpcodeConditional Jump Direct Immediate Shift Mnemonic Direct Immediate Indirect Indexed Special Mnemonic Direct Immediate IndirectPTS Mnemonic Direct Immediate Indirect Table A-9. Instruction Execution Times in State Times Arithmetic Group IndirectNormal Autoinc Short Long Reg Mem Mem Reg Mnemonic Direct Immed Normal Autoinc Short Long Reg Mem DIV Divb Divu DivubLogical Stack Register Indirect Normal Autoinc ShortReg Mem Autoinc Short Long Reg LDB Ldbse Ldbze STB XCH XchbAutoinc Short Long Ljmp Sjmp Tijmp Call Memory Indirect Indexed Mnemonic Direct Normal Autoinc Short LongConditional Jump Mnemonic Shift Mnemonic Direct Indirect IndexedClrc Clrvt Idlpd NOP RST Setc SkipPage Signal Descriptions Page Signal Name Changes Functional Groupings of SignalsTable B-1. Signal Name Changes New Name Table B-2 XC196MC Signals Arranged by Functional Categories Figure B-1 XC196MC 64-lead Shrink DIP Sdip Package U8XC196MC Figure B-2 XC196MC 84-lead Plcc Package X8XC196MC Figure B-3 XC196MC 80-lead Shrink EIAJ/QFP Package Table B-3 XC196MD Signals Arranged by Functional Categories P7.7/FREQOUT Figure B-4 XC196MD 84-lead Plcc Package X8XC196MD Figure B-5 XC196MD 80-lead Shrink EIAJ/QFP Package Table B-4 XC196MH Signals Arranged by Functional Categories EA# Extint NMI ONCE# RESET# XTAL1 XTAL2P2.7/SCLK1#/BCLK1 Figure B-6 XC196MH 64-lead Shrink DIP Sdip Package X8XC196MH Figure B-7 XC196MH 84-lead Plcc Package Signal Descriptions Figure B-8 XC196MH 80-lead Shrink EIAJ/QFP Package Table B-6. Signal Descriptions Table B-5. Description of Columns of Table B-6Column Heading Description Name BCLK10 CCR0.1 CCR1.2 BuswidthCOMP1/P2.5/PACT#, COMP2/P2.6/CPVER, COMP3/P2.7MC, MD Command that invoked the power-saving mode System using a clip-on emulator P5.7/BUSWIDTH Slave programming Auto programmingPMODE.30 Programming Start SCLK10# Shift Clock 0 MH only Default Conditions Table B-7. Definition of Status Symbols Table B-8 XC196MC and MD Default Signal ConditionsPort Signals Alternate During Upon RESET# Functions RESET# Active NMI WK0 RESET# WG2 WK1WG3 WK1 PWM0 WK0 Table B-9 XC196MH Default Signal Conditions RESET#Port Signals Alternate During Upon Osc output Registers Page Table C-1. Modules and Related Registers CPU8XC196MC, MH, x = Table C-2. Register Name, Address, and Reset Status Xxxx EPA2TIME MC, MD Xxxx EPA3TIME MC, MDXxxx EPA4TIME MD Xxxx EPA5TIME MD P7PIN MD Xxxx P1REG MH1FFD P5REG MC, MD Xxxx TIMER1 TIMER2Usfr MC, MD Usfr MH Xxxx Watchdog Adcommand Adresult Read Adresult Write Adtest Adtime CCR0 ALE CCR1 IRC2 IRC1 IRC0 COMPxCON Comp xCON Address Table C-3 = 0-3 8XC196MC, MH For EPA capture/compare channels 0, 2 Table C-3. COMPxTIME Addresses and Reset Values Register Address Reset ValueCOMPxTIME Comp xTIME Address EPAxCON EPAxCON Address Table C-4 = 0-1 8XC196MH = 0-3 8XC196MC x = 0-5 8XC196MD Table C-4. EPAxCON Addresses and Reset Values = 0-3 8XC196MC = 0-5 8XC196MD Table C-5. EPAxTIME Addresses and Reset Values EPA Timer ValueEPAxTIME EPAxTIME = 0-1 8XC196MH x = 0-3 8XC196MC x = 0-5 8XC196MD Freqcnt Freqgen Gencon Intmask OVRTM† INTMASK1 Intpend INTPEND1 Onesreg OnesregFfffh One Table C-6. PxDIR Addresses and Reset Values PxDIR= 1 MH = 2, 5 M Table C-7. PxMODE Addresses and Reset Values PxMODE= 1 MH = 2, 5 Mx PIN7 PIN6 PIN5 PIN4 Table C-8. Special-function Signals for Ports 1, 2, 5 Pin Special-function SignalPort 8XC196MC, MD Table C-9. PxPIN Addresses and Reset Values PxPIN Table C-10. PxREG Addresses and Reset Values PxREGPxREG = 2-5 8XC196MC = 2-5, 7 8XC196MD x = 1-5 8XC196MH = 2-5 M Pimask Pimask Pipend Pipend PPW PPW150 Ppwvalue PSW PSWPSE PSW Ptssel Ptssrv Pwmcount Pwmperiod PWMxCONTROL PWM xCONTROL Address 1FB0H, 1FB2H SBUFxRX SBUFxRX Address 1F80H, 1F88H = 0-1 8XC196MH8XC196MH Data Received Bit SBUFxTX Sbuf xTX Address 1F82H, 1F8AH = 0-1 8XC196MH8XC196MH Data to Transmit Bit Stack Pointer 150 Stack Pointer SPxBAUD SPxCON SPxCON Address 1F83H, 1F8BH = 0-1 8XC196MH SPxSTATUS T1CONTROL Timer 1 Reload Value T1RELOADT1RELOAD T2CONTROL TIMERx Timer Address 1F7AH1F7EH Usfr Watchdog Watchdog0AH WGCOMPx Wgcontrol Wgcounter Wgoutput Port Wgoutput Waveform Generator Wgoutput Waveform Generator Table C-11. Output Configuration Output Values Output Polarities WG x# Wgprotect Wgreload WSR Byte WindowsRegister Mnemonic 00E0-00FFH 00C0-00FFH 00E0-00FFH 00C0-00FFH 0080-00FFH Location T2CONTROL 1F7CH 7BH 00FCH 3DH 1EH TIMER1 † 1F7AH 00FAH 1EH 00FAH TIMER2 † 1F7EH 7BH 00FEH 3DH WGCOMP1 1FC2HPWM0CONTROL 1FB0H 7DH PWM1CONTROL 1FB2H 7DH Zeroreg ZeroregZero Page Glossary Page Glossary Characteristic DOUBLE-WORD LONG-INTEGER LSB Otprom PTS PWM SFR Special interrupt WDT Page Index Page Index Index-2 Index-3 Index-4 Index-5 Index-6 Index-7 Index-8 Index-9 Index-10 Index-11 Index-12 Index-13 Index-14