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Intel 8XC196MD, 8XC196MH, 8XC196MC manual BUS-CONTROL Modes, Bus-control Modes

Models: 8XC196MD 8XC196MH 8XC196MC

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	INTERFACING WITH EXTERNAL MEMORY
	Table 15-5. READY Signal Timing Definitions (Continued)

Symbol	Definition

††	READY Hold after ALE Low
TLLYX	READY Hold after ALE Low
	Minimum time the level of the READY signal must be valid after ALE falls. If the maximum
	value is exceeded, additional wait states will occur.

††	ALE Low to READY Setup
TLLYV	ALE Low to READY Setup
	Maximum time the external device has to deassert READY after ALE falls.

TQVWH	Data Valid to WR# High
	Time between data being valid on the bus and the microcontroller deasserting WR#.

TRLDV	RD# Low to Input Data Valid
	Maximum time the memory system has to output valid data after the microcontroller asserts
	RD#.

TRLRH	RD# Low to RD# High
	RD# pulse width.

TWLWH	WR# Low to WR# High
	WR# pulse width.

TXTAL1	1/FXTAL1
	All AC timings are referenced to TXTAL1.

†This specification applies to the 8XC196MC, MD microcontrollers only.

††This specification applies to the 8XC196MH microcontroller only.

15.5 BUS-CONTROL MODES

The ALE and WR bits (CCR0.3 and CCR0.2) define which bus-control signals will be generated during external read and write cycles. Table 15-6 lists the four bus-control modes and shows the CCR0.3 and CCR0.2 settings for each.

.

Table 15-6. Bus-control Modes

	Bus-control Mode	Bus-control Signals	CCR0.3	CCR0.2
	Bus-control Mode	Bus-control Signals	(ALE)	(WR)
			(ALE)	(WR)

	Standard Bus-control Mode	ALE, RD#, WR#, BHE#	1	1

	Write Strobe Mode	ALE, RD#, WRL#, WRH#	1	0

	Address Valid Strobe Mode	ADV#, RD#, WR#, BHE#	0	1

	Address Valid with Write Strobe Mode	ADV#, RD#, WRL#, WRH#	0	0

15-21

Image 336

Intel 8XC196MD, 8XC196MH, 8XC196MC BUS-CONTROL Modes, Bus-control Modes, Bus-control Mode Bus-control Signals CCR0.3 CCR0.2

Contents

8XC196MC, 8XC196MD, 8XC196MH Microcontroller User’ Manual We Value Your Opinion Page 8XC196MC, 8XC196MD, 8XC196MH Microcontroller User’s Manual Intel Corporation Contents Chapter Memory Partitions Contents 8XC196MC, MD, MH USER’S Manual PWM Signals and Registers Functional Overview Programming the Frequency GeneratorApplication Example Programming the Waveform GeneratorChapter Event Processor Array EPA Chapter Minimum Hardware Considerations Chapter Programming the Nonvolatile Memory Appendix C Registers Glossary Index Figures 10-5 15-9 Ready Timing Diagram One Wait State 8XC196MH 15-21 Tables 11-12 16-7 Pmode Values Guide to This Manual Page Manual Contents Chapter Guide to this ManualSpecial Operating Modes Notational Conventions and Terminology Assert and deassertNumbers Related Documents Handbooks and Product Information Application Notes, Application Briefs, and Article ReprintsTitle Order Number MCS 96 Microcontroller Datasheets Commercial/Express MCS 96 Microcontroller Datasheets AutomotiveThis Page Left Intentionally Blank Guide to this Manual This Page Left Intentionally Blank World Wide Web Technical SupportProduct Literature Page Architectural Overview Page Microcontroller Features Typical ApplicationsFeatures of the 8XC196Mx Product Family Functional OverviewOtprom SIO PWMROM PTS EPA PWM WDT SIOCPU RAMCPU Control Register FileRegister Arithmetic-logic Unit Ralu Code Execution Instruction FormatInterrupt Service Memory Interface UnitInternal Timing Clock CircuitryInternal Peripherals State Times at Various Frequencies1 I/O Ports Serial I/O SIO PortEvent Processor Array EPA and Timer/Counters Pulse-width Modulator PWMFrequency Generator Waveform GeneratorWatchdog Timer Reducing Power ConsumptionTesting the Printed Circuit Board Analog-to-digital ConverterProgramming the Nonvolatile Memory Programming Considerations Page Overview of the Instruction SET Operand Type DefinitionsOperand Type No. Signed Possible Values Addressing RestrictionsBIT Operands Byte OperandsSHORT-INTEGER Operands Word OperandsInteger Operands DOUBLE-WORD OperandsLONG-INTEGER Operands Converting OperandsConditional Jumps Floating Point OperationsAddressing Modes Direct Addressing Immediate AddressingIndirect Addressing Definition of Temporary RegistersIndexed Addressing Indirect Addressing with AutoincrementIndirect Addressing with the Stack Pointer Short-indexed AddressingLong-indexed Addressing Zero-indexed AddressingAssembly Language Addressing Mode Selections Using RegistersSoftware Standards and Conventions Addressing 32-bit Operands Linking SubroutinesSoftware Protection Features and Guidelines 8XC196MC, MD, MH USER’S Manual Memory Partitions Page Memory Partitions External Devices Memory or I/OProgram and Special-purpose Memory Program Memory Memory MapDevice Description Addressing ModesSpecial-purpose Memory Special-purpose Memory AddressesReserved Memory Locations Interrupt and PTS VectorsChip Configuration Bytes CCBs Special-function Registers SFRsSecurity Key Memory-mapped SFRs Peripheral SFRsEPA and Timer SFRs Peripheral SFRs 8XC196MCPort 2 SFRs SFRsPeripheral SFRs 8XC196MD Ports 2 and 7 SFRsPeripheral SFRs 8XC196MH Port 0 and 2 SFRsPort 1 SFRs Serial I/O Port SFRsRegister File Memory Map AddressRegister File Memory Addresses General-purpose Register RAMStack Pointer SP Device and Hex Address Range Description Addressing ModesCPU Special-function Registers SFRs CPU SFRsAddress High Odd Byte Low Even Byte Windowing 8XC196MC,MD02FFH 01FFH 00FFHSelecting a Window WSRBit Function Number WSR Value for PeripheralsAddressing a Location Through a Window 10. Selecting a Window of the Upper Register File11. Windows 12. Windowed Base AddressesBase WSR Value WSR Value for Peripheral SFRs2.1 32-byte Windowing Example 2.2 64-byte Windowing Example2.3 128-byte Windowing Example Unsupported Locations Windowing ExampleUsing the Linker Locator to Set Up a Window ?WSRThis listing shows the disassembled code Windowing and Addressing Modes LDB WSR, #12HPage Standard and PTS Interrupts Page Chapter Standard and PTS Interrupts Overview of InterruptsFlow Diagram for PTS and Standard Interrupts Interrupt Signals and Registers Interrupt SignalsInterrupt and PTS Control and Status Registers Interrupt Sources and Priorities Pipend 1FBEHPtssel PtssrvInterrupt Controller PTS Service Interrupt Sources, Vectors, and PrioritiesInterrupt Source Mnemonic Name Vector Priority Special Interrupts External Interrupt PinUnimplemented Opcode Software TrapMultiplexed Interrupt Sources Waveform Generator Protection CircuitryFlow Diagram for the Ovrtm Interrupt End-of-PTS Interrupts Interrupt LatencySituations that Increase Interrupt Latency Calculating Latency Standard Interrupt LatencyStandard Interrupt Response Time PTS Interrupt Latency PTS Mode Execution Time in State Times Programming the InterruptsExecution Times for PTS Cycles Standard and PTS Interrupts Ptssel 8XC196MC8XC196MD Bit FunctionIntmask COMP2 EPA2 COMP1 EPA1 COMP3 COMP0 EPA0 OvrtmBit Mnemonic Interrupt Standard Vector COMP2 MC, MDINTMASK1 NMI ExtintNMI Extint EPA5 NMI Extint SPI COMP3 EPA3 COMP4 EPA4 RI1 RI0 TI1 TI0Pimask 8XC196MC 8XC196MDBit Function Number Mnemonic Modifying Interrupt Priorities PimaskOVRTM1 Standard and PTS Interrupts Determining the Source of an Interrupt 10. Interrupt Pending Intpend Register Intpend11. Interrupt Pending 1 INTPEND1 Register INTPEND112. Peripheral Interrupt Pending Pipend Register PipendInitializing the PTS Control Blocks PipendSpecifying the PTS Count 14. PTS Service Ptssrv Register PtssrvSelecting the PTS Mode Single Transfer ModePtscon PTS Single Transfer Mode Control Block Ptsdst H Ptsdst L Ptssrc H Ptssrc L Ptscon PtscountRegister Location Function Ptsdst Ptscb +Standard and PTS Interrupts Block Transfer Mode Single Transfer Mode PtscbBlock Transfer Mode Ptscb PTS Block Transfer Mode Control Block Ptsblock Ptscb +5 A/D Scan Mode PTS A/D Scan Mode Control Block A/D Scan Mode Command/Data Table Address Contents5.1 A/D Scan Mode Cycles 5.2 A/D Scan Mode ExampleCommand/Data Table Example A/D Scan Mode Ptscb ExamplePTSPTR2 H = 1FH PTSPTR2 L = AAH Ptscount = 04H5.3 A/D Scan Mode Example 10. Command/Data Table Example11. A/D Scan Mode Ptscb Example Serial I/O ModesPTS Serial I/O Mode Control Block 1 8XC196MC, MD SA1 SA0 MAJPtsvec Baud EparegSA1 SA0 †8XC196MC, MD, MH USER’S Manual PTS Serial I/O Mode Control Block 2 8XC196MC, MD Port Mask RegisterPort Address Pointer high byte Data PTSCON1Rpar PTS Serial I/O Mode Control Block 8XC196MC, MD Register Location FunctionPortreg 8XC196MC, MD, MH USER’S Manual 13. Ssio Transmit Mode PTSCBs PTSCB1 PTSCB2Txddone = Synchronous SIO Receive Mode Example 23. Synchronous SIO Receive Timing14. Ssio Receive Mode PTSCBs Clrb RxddoneStandard and PTS Interrupts Rxddone = 25. Asynchronous SIO Transmit Timing 15. Asio Transmit Mode PTSCBs Standard and PTS Interrupts End-Of-PTS Interrupt Save Critical Data Is PTS Asynchronous SIO Receive Mode Example 27. Asynchronous SIO Receive Timing16. Asio Receive Mode PTSCBs Samptime = 01HPortreg H = 1FH P2PIN Standard and PTS Interrupts End-Of-PTS Interrupt Ports Page I/O Ports Overview Device I/O PortsPort Bits Type Direction Associated Peripherals Standard Input-only Port Pins INPUT-ONLY Ports 1 MC, MD onlyStandard Input-only Port Operation Input-only Port Registers1FDAH MH P1PIN MC, MDStandard Input-only Port Considerations Bidirectional Ports 1 MH ONLY, 2, 5, and 7 MD onlyBidirectional Port Pins Port Pin Special-function Associated SignalsBidirectional Port Operation Bidirectional Port Control and Status RegistersPorts Bidirectional Port Structure Bidirectional Port Pin Configurations Logic Table for Bidirectional Ports in I/O ModeSfdir 8XC196MC, MD, MH USER’S Manual Bidirectional Port Pin Configuration Example Control Register Values for Each ConfigurationPort Configuration Example Bidirectional Port Considerations HZ1P5.1/INST Ports 3 and 4 Pins Port Pins Special-functionBidirectional Ports 3 and 4 ADDRESS/DATA BUS 12. Ports 3 and 4 Control and Status RegistersBidirectional Ports 3 and 4 Address/Data Bus Operation Address/Data Bus Ports 3 and 4 StructureUsing Ports 3 and 4 as I/O Design Considerations for Ports 3Standard OUTPUT-ONLY Port 13. Logic Table for Ports 3 and 4 as Open-drain I/OConfiguring Output-only Port Pins 14. Standard Output-only Port PinsOutput-only Port Operation 15. Output-only Port Control RegisterReset State 0000H Wgoutput Port Address1FC0H OP1 OP0Reset State 0000H Wgoutput PortPage Serial I/O SIO Port Page SIO Block Diagram Serial I/O SIO Port Functional OverviewSerial I/O Port Signals and Registers Serial Port SignalsSerial Port Control and Status Registers P1DIR 1F9BH P1PIN 1F9FHP1REG 1F9DH Serial Port Modes Synchronous Modes Modes 0 ModeMode 0 Timing Asynchronous Modes Modes 1, 2, Serial Port Frames for Mode Mode 2 and 3 Timings Multiprocessor CommunicationsConfiguring the Serial Port Pins Programming the Serial PortProgramming the Control Register SP xCON Address 1F83H, 1F8BH = 0-1 8XC196MHBit Function Programming the Baud Rate and Clock Source ClksrcBV7 BV9 BV8Baudvalue = BclkSPxBAUD Values When Using XTAL1 at 16 MHz Enabling the Serial Port Interrupts80CFH E82BHDetermining Serial Port Status RPE/RB8 TXERPE/RB8 8XC196MC, MD, MH USER’S Manual Frequency Generator Page Chapter Frequency Generator Frequency Generator Signal Frequency Generator Control and Status RegistersPort Frequency Configuring the Output Programming the Frequency GeneratorProgramming the Frequency FreqgenDetermining the Current Value of the Down-counter Application ExampleFreqcnt Frequency Generator 0FAH Xmitbuf Dsb Bufsize Block of data to send Shiftreg Stb temp,freqgen0 Into freq gen Frequency Generator Page Waveform Generator Page Chapter Waveform Generator Waveform Generator Functional OverviewWaveform Generator Block Diagram Waveform Generator Signals and Registers Waveform Generator SignalsWaveform Generator Control and Status Registers Waveform Generator Operation Timebase GeneratorPhase Driver Channels Control and Protection CircuitryRegister Buffering and Synchronization Protection CircuitryOperating Modes Register Updates Event ModeOperation in Center-aligned and Edge-aligned Modes Step Center-aligned Modes Edge-aligned ModesCenter-aligned Modes Center-aligned Modes Counter OperationCenter-aligned Modes Output Operation Edge-Aligned Modes Edge-aligned Modes Counter Operation Configuring the Outputs Output ConfigurationProgramming the Waveform Generator Wgoutput Waveform Generator OP1 OP0 Sync PE7PE6 OP18XC196MC, MD, MH USER’S Manual Wgprotect F0HE0H 8XC196MC, MD 8XC196MH Bit Function Number MnemonicSpecifying the Carrier Period and Duty Cycle WgreloadReload 150 ReloadWgcomp Address 1FC2H,1FC4H,1FC6HWgcontrol DT7 DT6 DT5 DT4 DT9 DT8 DT3 DT2 DT1 DT0Wgcounter = Wgreload Determining the Waveform GENERATOR’S Status Enabling the Waveform Generator InterruptsWgcounter XxxxhDesign Considerations Dead Time and Duty CycleWgcount WGCOUNT= WgcompProgramming Example Ph3 Dsw P6.4,5 config Waveform Generator Temp1,WGOUTPUT0 Now store it Ret Demo board PI interrupt Page Pulse-width Modulator Page Chapter PULSE-WIDTH Modulator PWM Functional OverviewPWM Signals and Registers PWM SignalsPWM Operation PWM Control and Status RegistersPEx Pin Output Programming the Frequency and Period E6HFFH PWM Output Frequencies Fpwm PwmperiodProgramming the Duty Cycle Pwmperiod +Sample Calculations Reading the Current Value of the Down-counterPWM xCONTROL Address 10-3 PWM Output Alternate Port Function PWM Output Enabled When Enabling the PWM OutputsPWM Output Alternate Functions PwmcountWaveform Generator Output Configuration Wgoutput Register D/A Buffer Block Diagram Generating Analog OutputsEvent Processor Array EPA Page EPA Functional Overview EPA ChannelsDevice Capture/Compare Channels Compare-only Channels COMP30EPA and TIMER/COUNTER Signals and Registers EPA and Timer/Counter SignalsEPA Control and Status Registers P0PIN 1FA8H P1PIN 1FA9HTIMER/COUNTER Functional Overview TIMER1 1F7AHTIMER2 1F7EH T1RELOADEPA Timer/Counters Cascade Mode Timer 2 Only Quadrature Clocking ModesState of Xinternal State of Yinternal Count Direction T1DIRQuadrature Mode Timing and Count EPA Channel Functional OverviewOperating in Capture Mode A Single EPA Capture/Compare ChannelEPA Simplified Input-capture Structure Action Taken When a Valid Edge Occurs Overwrite Bit Status Action Taken When a Valid Edge OccursEPA Overruns EPAxCON.0Operating in Compare Mode Preventing EPA OverrunsGenerating a Low-speed PWM Output Generating the Highest-speed PWM Output Programming the EPA and TIMER/COUNTERS Configuring the EPA and Timer/Counter SignalsProgramming the Timers Prescaler Divisor Resolution † T1CONTROLClock Source Direction Source Prescaler Resolution † T2CONTROLExample EPA Control Register Settings for Channels 1, 3, or Mode WGR ROT ON/RTProgramming the Capture/Compare Channels Capture Mode Event Compare Mode ActionEPAxCON = 0-1 8XC196MH x = 0-3 8XC196MC x = 0-5 8XC196MD = 0, 2 = 1, 3EPA xCON Address = 0, 2For EPA capture/compare channels 0, 2 For EPA capture/compare channels 1, 3Capture Mode on Compare Mode RT= 0-3 8XC196MC, MH = 0-5 8XC196MD Reset State 00H Programming the Compare-only ChannelsComp xCON Address WGR ROTEnabling the EPA Interrupts Determining Event Status Analog-to-digital Converter PageNum-38 12.1 A/D Converter Functional Overview Angnd12.2 A/D Converter Signals and Registers A/D Converter PinsPort Pin Signal Description A/D Control and Status Registers12.3 A/D Converter Operation P1PIN MC,MDProgramming the A/D Converter Programming the A/D Test Register AdtestOFF1 OFF0 Programming the A/D Time Register Adresult WriteProgramming the A/D Command Register AdtimeAdcommand M1 M0 ModeEnabling the A/D Interrupt ACH3 ACH2 ACH1 ACH0Determining A/D Status and Conversion Results Adresult ReadADRLT90 Designing External Interface Circuitry Idealized A/D Sampling CircuitryMinimizing the Effect of High Input Source Resistance Suggested A/D Input Circuit Understanding A/D Conversion Errors Using Mixed Analog and Digital Inputs12-14 Ideal A/D Conversion Characteristic 10. Actual and Ideal A/D Conversion Characteristics 12-17 11. Terminal-based A/D Conversion Characteristic Minimum Hardware Considerations Page Minimum Required Signals RESET#Minimum Connections I/O Port Configuration Guide Port Where to Find Configuration InformationUnused Inputs 13.1.2 I/O Port Pin ConnectionsMinimum Hardware Connections Applying and Removing Power Noise Protection TipsON-CHIP Oscillator Circuitry On-chip Oscillator CircuitExternal Crystal Connections Using AN External Clock Source External Clock ConnectionsResetting the Device Reset Timing SequenceGencon Rsts DR0Rsts DROGenerating an External Reset Internal Reset Circuitry10. Minimum Reset Circuit Issuing the Reset RST Instruction Enabling the Watchdog TimerIssuing an Illegal Idlpd Key Operand Generating Wait StatesSelecting the Watchdog Reset Interval 8XC196MH only First Byte Second Byte Reset Interval1EH E1H 1EH A1HPage Special Operating Modes Page Special Operating Mode Signals and Registers Operating Mode Control SignalsPort Pin Signal Type Description ClkoutOperating Mode Control and Status Registers Port Pin Signal Type Description NameONCE# CCR0Reducing Power Consumption P1MODEMHP7MODEMD 1FD1H P1REG MH 1F9DHIdle Mode Clock Control During Power-saving ModesPowerdown Mode Enabling and Disabling Powerdown ModeEntering Powerdown Mode Exiting Powerdown ModeGenerating a Hardware Reset Driving the VPP Pin LowAsserting the External Interrupt Signal External RC Circuit Selecting R1 and C1Typical Voltage on the VPP Pin While Exiting Powerdown Once Mode Reserved Test Modes Page Interfacing with External Memory Page External Memory Interface Signals and Registers External Memory Interface SignalsSignal Port Pin Type Description Name ADV#Bytes Accessed BHE# AD0CCR0.1 CCR1.2 BuswidthSignal Port Pin EA#WR# External Memory Interface Registers WRH#WRL# Register Address Description MnemonicChip Configuration Registers and Chip Configuration Bytes P5REG = 11XX XxxxbBHE#/WRH# † 15-6 CCR0 LOC1 LOC0 IRC1 IRC0 ALE BW0LOC1 LOC0 IRC2 IRC1 IRC0CCR0 ALEBW1 BW0 CCR1 WDE BW1 IRC2WDE BUS Width and Multiplexing CCR1Multiplexing and Bus Width Options Buswidth Timing Diagram 8XC196MC, MD Buswidth Signal Timing Definitions Symbol DefinitionTiming Requirements for Buswidth 15.3.2 16-bit Bus Timings Timings for 16-bit Buses 15.3.3 8-bit Bus Timings Wait States Ready Control Timings for 8-bit Buses15-18 Ready Timing Diagram One Wait State 8XC196MC, MD Address Valid to Ready Setup Bus-control Mode Bus-control Signals CCR0.3 CCR0.2 BUS-CONTROL ModesBus-control Modes Standard Bus-control Mode BHE# WR# AD0CS# ALE OE# WE# RD# WR#Buswidth CS# Eprom RAMOE# WE# RD# WR# Write Strobe Mode 14. Write Strobe Mode15 -bit System with Writes to Byte-wide RAMs OE# OE# WE# RD# WRH# WRL#Address Valid Strobe Mode 16. Address Valid Strobe Mode18 -bit System with Flash Eprom OE# RD#Address Valid with Write Strobe Mode 20. Timings of Address Valid with Write Strobe ModeSystem BUS AC Timing Specifications VCC BuswidthWRH# WRL# CS# WE# CS#22. System Bus Timing Explanation of AC Symbols AC Timing Symbol Definitions SignalsExternal Memory Systems Must Meet These Specifications AC Timing DefinitionsMicrocontroller Meets These Specifications Address Setup to ALE/ADV# Low15-35 Page Programming Nonvolatile Memory Page Programming the Nonvolatile Memory Programming MethodsOtprom Memory MAP Security Features Controlling Access to Internal MemoryC196Mx Otprom Memory Map Address Range Description HexControlling Access to the Otprom During Normal Operation Memory Protection for Normal Operating ModeControlling Access to the Otprom During Programming Modes Read Protect Write Protect Protection StatusMemory Protection Options for Programming Modes Security KeyPccb CCB Controlling Fetches from External Memory Uprom Programming Values and Locations for Slave Mode UsfrTo set this bit Write this value To this location Programming Pulse Width PpwvaluePPW BitBitFunction Number MnemonicModified QUICK-PULSE Algorithm Example Ppwvalue Calculations8XC196MC, MD 8XC196MH Two 250-µs pulses required Ppwvalue =Modified Quick-pulse Algorithm Programming Mode Pins Special Program Port PinPROG# AINC#Cpver PACT#Selecting the Programming Mode Entering Programming ModesPmode Values Power-up and Power-down Sequences Power-up SequencePower-down Sequence Slave Programming Mode Reading the Signature Word and Programming VoltagesSlave Programming Circuit and Memory Map Device Signature Word and Programming VoltagesDevice Signature Word Programming VCC Location ValueSlave Programming Mode Memory Map Operating EnvironmentDescription Address Comments CCR1, CCR0 LOC1 LOC0 IRC1 IRC0 WDE BW1 IRC2Bit Mnemonic Function Slave Programming Routines Address/Command Decoding Routine Program Word Routine Program Word Waveform 10. Dump Word Routine Timing Mnemonics 10. Timing MnemonicsMnemonicDescription Auto Programming Mode Auto Programming Circuit and Memory MapMnemonic Description 12. Auto Programming Circuit Address Internal Address Using Output from Address Internal Address UsingAuto Programming Routine 11 XC196MC/MD Auto Programming Memory Map13. Auto Programming Routine Auto Programming Procedure ROM-dump Mode Pccb and Uprom Programming 8XC196MH only14. Pccb and Uprom Programming Circuit Pins Pccb Programming Uprom Programming RUN-TIME Programming13. Pccb and Uprom Programming Values PMODE30 0DH15. Run-time Programming Code Example Page Instruction Set Reference Page Appendix a Instruction SET Reference Table A-1. Opcode Map Left Half OpcodeTable A-1. Opcode Map Right Half Table A-2. Processor Status Word PSW Flags Value of Bits Shifted OffInstruction Quotient Stored Flag Set if Quotient is Table A-4. PSW Flag Setting Symbols Symbol DescriptionInstruction Jumps to Destination if Continues if Table A-5. Operand Variables Variable DescriptionPSW Flag Settings Table A-6. Instruction SetMnemonic Operation C V VT STInstruction Format Dest ← Dest and SRCAndb PTRS, Cntreg CountCount ← Cntreg Loop Srcptr ← Ptrs Dstptr Dstptr ← Srcptr Ptrs ← Srcptr +Count ← Count DestClear BYTE. Clears the value Mnemonic Operation Instruction Format ← Dest MOD SRC Dest MOD SRCDjnz Decrement and Jump if not Zero Djnzw Decrement and Jump if not ZeroDpts Disable Peripheral Transaction Epts Enable Peripheral TransactionEpts EXT SIGN-EXTEND Integer Into LongExtb SIGN-EXTEND SHORT-INTEGER Into Increment BYTE. Increments the value Byte operand by JGE Jump if Signed Greater than or JLE Jump if Signed Less than or Equal Negative flag is set, this instruction adds JNV Jump if Overflow Flag is Clear Jnvt Jump if OVERFLOW-TRAP Flag is JVT Jump if OVERFLOW-TRAP Flag is SET Load Byte SIGN-EXTENDED. Sign MUL MulbMulu MulubInteger operand SRC, DestDest ← not Dest Dest ← Dest or SRCINTMASK1/WSR ← SP PSW/INTMASK ← SPSP ← PSW/INTMASK PSW/INTMASK ← SP ← INTMASK1/WSR INTMASK1 ←Scall Wreg, #count SHR Range of 0 to 31 1FH, inclusive. If Shral Arithmetic Right Shift Double Shrl Logical Right Shift DOUBLE-WORD SkipRightmost operand SUBSubb Subc Subtract Words with Borrow DEST, SRCSubc Subcb Subtract Bytes with Borrow DEST, SRCIndex and #MASK = Offset × Offset + Tbase = DestTijmp TBASE, INDEX, #MASK XOR Dest ← Dest XOR SRCTable A-7. Instruction Opcodes Hex Code Instruction MnemonicClrb Notb Negb Decb Extb Incb Shrb Shlb ShrabHex Code Hex Code 8XC196MC, MD, MH USER’S Manual Dpts Epts EF LcallDIV/DIVB/MUL/MULB Note Table A-8. Instruction Lengths and Hexadecimal Opcodes Arithmetic Group Direct Immediate Indirect Indexed MnemonicSubc Subcb Logical Direct Immediate Indirect Stack Direct Immediate Indirect Indexed Mnemonic Opcode LengthData Direct Jump DirectCall Direct Immediate Indirect Indexed Mnemonic Length OpcodeConditional Jump Direct Immediate Shift Mnemonic Direct Immediate Indirect Indexed Special Mnemonic Direct Immediate IndirectPTS Mnemonic Direct Immediate IndirectTable A-9. Instruction Execution Times in State Times Arithmetic Group IndirectNormal Autoinc Short Long Reg Mem Mem RegMnemonic Direct Immed Normal Autoinc Short Long Reg Mem DIV Divb Divu DivubLogical Stack Register Indirect Normal Autoinc ShortReg Mem Autoinc Short Long Reg LDB Ldbse Ldbze STB XCH XchbAutoinc Short Long Ljmp Sjmp TijmpCall Memory Indirect Indexed Mnemonic Direct Normal Autoinc Short LongConditional Jump Mnemonic Shift Mnemonic Direct Indirect IndexedClrc Clrvt Idlpd NOP RST Setc SkipPage Signal Descriptions Page Signal Name Changes Functional Groupings of SignalsTable B-1. Signal Name Changes New NameTable B-2 XC196MC Signals Arranged by Functional Categories Figure B-1 XC196MC 64-lead Shrink DIP Sdip Package U8XC196MCFigure B-2 XC196MC 84-lead Plcc Package X8XC196MCFigure B-3 XC196MC 80-lead Shrink EIAJ/QFP Package Table B-3 XC196MD Signals Arranged by Functional Categories P7.7/FREQOUTFigure B-4 XC196MD 84-lead Plcc Package X8XC196MDFigure B-5 XC196MD 80-lead Shrink EIAJ/QFP Package Table B-4 XC196MH Signals Arranged by Functional Categories EA# Extint NMI ONCE# RESET# XTAL1 XTAL2P2.7/SCLK1#/BCLK1 Figure B-6 XC196MH 64-lead Shrink DIP Sdip Package X8XC196MHFigure B-7 XC196MH 84-lead Plcc Package Signal Descriptions Figure B-8 XC196MH 80-lead Shrink EIAJ/QFP PackageTable B-6. Signal Descriptions Table B-5. Description of Columns of Table B-6Column Heading Description Name BCLK10 CCR0.1 CCR1.2 BuswidthCOMP1/P2.5/PACT#, COMP2/P2.6/CPVER, COMP3/P2.7MC, MD Command that invoked the power-saving mode System using a clip-on emulator P5.7/BUSWIDTH Slave programming Auto programmingPMODE.30 Programming Start SCLK10# Shift Clock 0 MH only Default Conditions Table B-7. Definition of Status Symbols Table B-8 XC196MC and MD Default Signal ConditionsPort Signals Alternate During Upon RESET# Functions RESET# ActiveNMI WK0 RESET# WG2 WK1WG3 WK1 PWM0 WK0Table B-9 XC196MH Default Signal Conditions RESET#Port Signals Alternate During UponOsc output Registers Page Table C-1. Modules and Related Registers CPU8XC196MC, MH, x = Table C-2. Register Name, Address, and Reset Status Xxxx EPA2TIME MC, MD Xxxx EPA3TIME MC, MDXxxx EPA4TIME MD Xxxx EPA5TIME MDP7PIN MD Xxxx P1REG MH1FFD P5REG MC, MDXxxx TIMER1 TIMER2Usfr MC, MD Usfr MH Xxxx WatchdogAdcommand Adresult Read Adresult Write Adtest Adtime CCR0 ALE CCR1 IRC2 IRC1 IRC0 COMPxCON Comp xCON Address Table C-3 = 0-3 8XC196MC, MHFor EPA capture/compare channels 0, 2 Table C-3. COMPxTIME Addresses and Reset Values Register Address Reset ValueCOMPxTIME Comp xTIME AddressEPAxCON EPAxCON Address Table C-4 = 0-1 8XC196MH = 0-3 8XC196MC x = 0-5 8XC196MDTable C-4. EPAxCON Addresses and Reset Values = 0-3 8XC196MC = 0-5 8XC196MDTable C-5. EPAxTIME Addresses and Reset Values EPA Timer ValueEPAxTIME EPAxTIME = 0-1 8XC196MH x = 0-3 8XC196MC x = 0-5 8XC196MDFreqcnt Freqgen Gencon Intmask OVRTM†INTMASK1 Intpend INTPEND1 Onesreg OnesregFfffh OneTable C-6. PxDIR Addresses and Reset Values PxDIR= 1 MH = 2, 5 MTable C-7. PxMODE Addresses and Reset Values PxMODE= 1 MH = 2, 5 Mx PIN7 PIN6 PIN5 PIN4Table C-8. Special-function Signals for Ports 1, 2, 5 Pin Special-function SignalPort 8XC196MC, MDTable C-9. PxPIN Addresses and Reset Values PxPINTable C-10. PxREG Addresses and Reset Values PxREGPxREG = 2-5 8XC196MC = 2-5, 7 8XC196MD x = 1-5 8XC196MH = 2-5 MPimask Pimask Pipend Pipend PPW PPW150 PpwvaluePSW PSWPSE PSW Ptssel Ptssrv Pwmcount Pwmperiod PWMxCONTROL PWM xCONTROL Address 1FB0H, 1FB2HSBUFxRX SBUFxRX Address 1F80H, 1F88H = 0-1 8XC196MH8XC196MH Data Received Bit SBUFxTX Sbuf xTX Address 1F82H, 1F8AH = 0-1 8XC196MH8XC196MH Data to Transmit Bit Stack Pointer 150 Stack PointerSPxBAUD SPxCON SPxCON Address 1F83H, 1F8BH = 0-1 8XC196MHSPxSTATUS T1CONTROL Timer 1 Reload Value T1RELOADT1RELOAD T2CONTROL TIMERx Timer Address 1F7AH1F7EH Usfr Watchdog Watchdog0AH WGCOMPx Wgcontrol Wgcounter Wgoutput Port Wgoutput Waveform Generator Wgoutput Waveform Generator Table C-11. Output Configuration Output Values Output Polarities WG x#Wgprotect Wgreload WSR Byte WindowsRegister Mnemonic 00E0-00FFH 00C0-00FFH00E0-00FFH 00C0-00FFH 0080-00FFH Location T2CONTROL 1F7CH 7BH 00FCH 3DH 1EH TIMER1 † 1F7AH 00FAH 1EH 00FAH TIMER2 † 1F7EH 7BH 00FEH 3DH WGCOMP1 1FC2HPWM0CONTROL 1FB0H 7DH PWM1CONTROL 1FB2H 7DHZeroreg ZeroregZero Page Glossary Page Glossary Characteristic DOUBLE-WORD LONG-INTEGER LSB Otprom PTS PWM SFR Special interrupt WDT Page Index Page Index Index-2 Index-3 Index-4 Index-5 Index-6 Index-7 Index-8 Index-9 Index-10 Index-11 Index-12 Index-13 Index-14