Intel 8XC196MC, 8XC196MD, 8XC196MH manual Index-4

8XC196MC, MD, MH USER’S MANUAL

re-enabling the compare event, 11-20, 11-22 reloading the waveform generator, 11-20,

11-23, C-16

resetting the timer in compare mode, 11-21 resetting the timers, 11-21, 11-23 selecting the capture/compare event, 11-19 selecting the compare event, 11-22 selecting the time base, 11-19, 11-22 selecting up or down counting, 11-16, 11-17 signals, 11-2

starting an A/D conversion, 11-20, 11-23, C-16

See also port 1, port 6, PWM, timer/counters EPA compare control x register, 11-22, C-15 EPA compare x time register, C-17

EPA control x register, 11-19, C-18 EPA time registers, C-21 EPA0_CON, C-68 EPA0_TIME, C-69 EPA1_CON, C-68 EPA1_TIME, C-69 EPA2_CON, C-69 EPA2_TIME, C-69 EPA3_CON, C-69 EPA3_TIME, C-69 EPA4_CON, C-69 EPA4_TIME, C-69

EPA5:0, 11-2, B-16

EPA5_CON, C-69

EPA5_TIME, C-69

EPTS instruction, 5-13, A-15, A-45, A-51, A-57 ESD protection, 6-3, 6-7, 13-5

Event processor array‚ See EPA

EXT instruction, A-2, A-15, A-41, A-47, A-52 EXTB instruction, A-2, A-16, A-41, A-47, A-52 EXTINT, 5-3, 14-7, B-16

and idle mode, 14-5

and powerdown mode, 14-6, 14-7 hardware considerations, 14-7

F

FaxBack service, 1-8 FE opcode

and inhibiting interrupts, 5-9 Floating point library, 3-4 Formulas

A/D conversion result, 12-9, 12-13

Index-4

A/D conversion time, 12-7 A/D error, 12-11

A/D sample time, 12-7 A/D series resistance, 12-10 A/D threshold voltage, 12-5 A/D voltage drop, 12-11

capacitor size (powerdown circuit), 14-10 PH1 and PH2 frequency, 2-8 programming pulse width, OTPROM, 16-8 programming voltage, 16-15

SIO baud rate, 7-13 state time, 2-8

FPAL-96, 3-4 FREQOUT, B-16 Frequency generator, 8-1–8-9

application example, 8-4–8-9 data encoding example, 8-5

block diagram, 8-1

infrared remote control application, 8-5 overview, 8-1–8-2

programming frequency, 8-3 output, 8-3

registers, 8-2 status, 8-4

Frequency generator count register, 8-4, C-22 Frequency register, 8-3, C-23

H

Handbooks, ordering, 1-6 Hardware

A/D converter considerations, 12-10–12-13 addressing modes, 3-5

auto programming circuit, 16-26 device considerations, 13-1–13-13 device reset, 13-8, 13-10, 13-11, 13-12 interrupt processor, 2-6, 5-1 memory protection, 16-7, 16-17 minimum configuration, 13-1

NMI considerations, 5-6 noise protection, 13-4

pin reset status, B-23, B-25 programming mode requirements, 16-13 reset instruction, 3-11

SIO port considerations, 7-8 slave programming circuit, 16-16 UPROM considerations, 16-7