Intel 8XC196MD, 8XC196MH, 8XC196MC manual Usfr

		REGISTERS
		USFR
USFR	Address:	1FF6H
	Reset State (MC, MD):	02H
	Reset State (MH):	XXH

The unerasable PROM (USFR) register contains two bits that disable external fetches of data and instructions and another that detects a failed oscillator. These bits can be programmed, but cannot be erased.

WARNING: These bits can be programmed, but can never be erased. Programming these bits makes dynamic failure analysis impossible. For this reason, devices with programmed UPROM bits cannot be returned to Intel for failure analysis.

7

— — — —

0

DEI DED — —

Bit	Bit	Function
Number	Mnemonic
7:4	—	Reserved; for compatibility with future devices, write zeros to these bits.
3	DEI	Disable External Instruction Fetch
		Setting this bit prevents the bus controller from executing external
		instruction fetches. Any attempt to load an external address initiates a
		reset.
2	DED	Disable External Data Fetch
		Setting this bit prevents the bus controller from executing external data
		reads and writes. Any attempt to access data through the bus controller
		initiates a reset.
1:0	—	Reserved; for compatibility with future devices, write zero to these bits.

C-57