Index and #MASK = Offset, × Offset + Tbase = Dest | Intel 8XC196MC

INSTRUCTION SET REFERENCE

Table A-6. Instruction Set (Continued)

Mnemonic

Operation

Instruction Format

TIJMP	TABLE INDIRECT JUMP. Causes execution
	to continue at an address selected from a
	table of addresses.
	The first word register, TBASE, contains the
	16-bit address of the beginning of the jump
	table. TBASE can be located in RAM up to
	FEH without windowing or above FFH with
	windowing. The jump table itself can be
	placed at any nonreserved memory location
	on a word boundary.
	The second word register, INDEX, contains
	the 16-bit address that points to a register
	containing a 7-bit value. This value is used to
	calculate the offset into the jump table. Like
	TBASE, INDEX can be located in RAM up to
	FEH without windowing or above FFH with
	windowing. Note that the 16-bit address
	contained in INDEX is absolute; it disregards
	any windowing that may be in effect when the
	TIJMP instruction is executed.
	The byte operand, #MASK, is 7-bit immediate
	data to mask INDEX. #MASK is ANDed with
	INDEX to determine the offset (OFFSET).
	OFFSET is multiplied by two, then added to
	the base address (TBASE) to determine the
	destination address (DEST X).
	[INDEX] AND #MASK = OFFSET
	(2 × OFFSET) + TBASE = DEST X
	PC ← (DEST X)

TIJMP TBASE, [INDEX], #MASK

(11100010) [INDEX] (#MASK) (TBASE)

NOTE: TIJMP multiplies OFFSET by two to provide for word alignment of the jump table.

PSW Flag Settings

Z		N		C	V	VT	ST
—	—		—	—	—	—

TRAP	SOFTWARE TRAP. This instruction causes
	an interrupt call that is vectored through
	location 2010H. The operation of this
	instruction is not affected by the state of the
	interrupt enable flag (I) in the PSW. Interrupt
	calls cannot occur immediately following this
	instruction.
	SP ← SP – 2
	(SP) ← PC
	PC ← (2010H)

			PSW Flag Settings
		Z	N	C	V	VT	ST
		—	—	— —	—	—

TRAP

(11110111)

NOTE: This instruction is not supported by assemblers. The TRAP instruction is intended for use by development tools. These tools may not support user-application of this instruction.

A-39

Image 428

Intel 8XC196MC, 8XC196MD, 8XC196MH manual Index and #MASK = Offset, × Offset + Tbase = Dest, Tijmp TBASE, INDEX, #MASK

Contents

8XC196MC, 8XC196MD, 8XC196MH Microcontroller User’ Manual We Value Your Opinion Page 8XC196MC, 8XC196MD, 8XC196MH Microcontroller User’s Manual Intel Corporation Contents Chapter Memory Partitions Contents 8XC196MC, MD, MH USER’S Manual PWM Signals and Registers Functional Overview Programming the Frequency GeneratorApplication Example Programming the Waveform Generator Chapter Event Processor Array EPA Chapter Minimum Hardware Considerations Chapter Programming the Nonvolatile Memory Appendix C Registers Glossary Index Figures 10-5 15-9 Ready Timing Diagram One Wait State 8XC196MH 15-21 Tables 11-12 16-7 Pmode Values Guide to This Manual Page Manual Contents Chapter Guide to this Manual Special Operating Modes Notational Conventions and Terminology Assert and deassert Numbers Related Documents Title Order Number Handbooks and Product InformationApplication Notes, Application Briefs, and Article Reprints MCS 96 Microcontroller Datasheets Commercial/Express MCS 96 Microcontroller Datasheets Automotive This Page Left Intentionally Blank Guide to this Manual This Page Left Intentionally Blank Product Literature World Wide WebTechnical Support Page Architectural Overview Page Microcontroller Features Typical Applications Features of the 8XC196Mx Product Family Functional OverviewOtprom SIO PWM ROM PTS EPA PWM WDT SIOCPU RAM Register Arithmetic-logic Unit Ralu CPU ControlRegister File Code Execution Instruction Format Interrupt Service Memory Interface Unit Internal Timing Clock Circuitry Internal Peripherals State Times at Various Frequencies 1 I/O Ports Serial I/O SIO Port Event Processor Array EPA and Timer/Counters Pulse-width Modulator PWMFrequency Generator Waveform Generator Watchdog Timer Reducing Power ConsumptionTesting the Printed Circuit Board Analog-to-digital Converter Programming the Nonvolatile Memory Programming Considerations Page Overview of the Instruction SET Operand Type DefinitionsOperand Type No. Signed Possible Values Addressing Restrictions BIT Operands Byte OperandsSHORT-INTEGER Operands Word Operands Integer Operands DOUBLE-WORD Operands LONG-INTEGER Operands Converting OperandsConditional Jumps Floating Point Operations Addressing Modes Direct Addressing Immediate AddressingIndirect Addressing Definition of Temporary Registers Indexed Addressing Indirect Addressing with AutoincrementIndirect Addressing with the Stack Pointer Short-indexed Addressing Long-indexed Addressing Zero-indexed Addressing Software Standards and Conventions Assembly Language Addressing Mode SelectionsUsing Registers Addressing 32-bit Operands Linking Subroutines Software Protection Features and Guidelines 8XC196MC, MD, MH USER’S Manual Memory Partitions Page Program and Special-purpose Memory Memory PartitionsExternal Devices Memory or I/O Program Memory Memory MapDevice Description Addressing Modes Special-purpose Memory Special-purpose Memory AddressesReserved Memory Locations Interrupt and PTS Vectors Security Key Chip Configuration Bytes CCBsSpecial-function Registers SFRs Memory-mapped SFRs Peripheral SFRs EPA and Timer SFRs Peripheral SFRs 8XC196MCPort 2 SFRs SFRs Peripheral SFRs 8XC196MD Ports 2 and 7 SFRs Peripheral SFRs 8XC196MH Port 0 and 2 SFRsPort 1 SFRs Serial I/O Port SFRs Register File Memory Map Address Register File Memory Addresses General-purpose Register RAMStack Pointer SP Device and Hex Address Range Description Addressing Modes Address High Odd Byte Low Even Byte CPU Special-function Registers SFRsCPU SFRs Windowing 8XC196MC,MD02FFH 01FFH 00FFH Selecting a Window WSRBit Function Number WSR Value for Peripherals Addressing a Location Through a Window 10. Selecting a Window of the Upper Register File 11. Windows 12. Windowed Base AddressesBase WSR Value WSR Value for Peripheral SFRs 2.1 32-byte Windowing Example 2.2 64-byte Windowing Example2.3 128-byte Windowing Example Unsupported Locations Windowing Example Using the Linker Locator to Set Up a Window ?WSR This listing shows the disassembled code Windowing and Addressing Modes LDB WSR, #12HPage Standard and PTS Interrupts Page Chapter Standard and PTS Interrupts Overview of Interrupts Flow Diagram for PTS and Standard Interrupts Interrupt and PTS Control and Status Registers Interrupt Signals and RegistersInterrupt Signals Interrupt Sources and Priorities Pipend 1FBEHPtssel Ptssrv Interrupt Source Mnemonic Name Vector Priority Interrupt Controller PTS ServiceInterrupt Sources, Vectors, and Priorities Special Interrupts External Interrupt PinUnimplemented Opcode Software Trap Multiplexed Interrupt Sources Waveform Generator Protection Circuitry Flow Diagram for the Ovrtm Interrupt Situations that Increase Interrupt Latency End-of-PTS InterruptsInterrupt Latency Calculating Latency Standard Interrupt Latency Standard Interrupt Response Time PTS Interrupt Latency Execution Times for PTS Cycles PTS Mode Execution Time in State TimesProgramming the Interrupts Standard and PTS Interrupts Ptssel 8XC196MC8XC196MD Bit Function Intmask COMP2 EPA2 COMP1 EPA1 COMP3 COMP0 EPA0 OvrtmBit Mnemonic Interrupt Standard Vector COMP2 MC, MD INTMASK1 NMI ExtintNMI Extint EPA5 NMI Extint SPI COMP3 EPA3 COMP4 EPA4 RI1 RI0 TI1 TI0 Bit Function Number Mnemonic Pimask8XC196MC 8XC196MD OVRTM1 Modifying Interrupt PrioritiesPimask Standard and PTS Interrupts Determining the Source of an Interrupt 10. Interrupt Pending Intpend Register Intpend 11. Interrupt Pending 1 INTPEND1 Register INTPEND1 12. Peripheral Interrupt Pending Pipend Register Pipend Initializing the PTS Control Blocks Pipend Specifying the PTS Count 14. PTS Service Ptssrv Register Ptssrv Ptscon Selecting the PTS ModeSingle Transfer Mode PTS Single Transfer Mode Control Block Ptsdst H Ptsdst L Ptssrc H Ptssrc L Ptscon PtscountRegister Location Function Ptsdst Ptscb + Standard and PTS Interrupts Block Transfer Mode Ptscb Block Transfer ModeSingle Transfer Mode Ptscb PTS Block Transfer Mode Control Block Ptsblock Ptscb + 5 A/D Scan Mode PTS A/D Scan Mode Control Block A/D Scan Mode Command/Data Table Address Contents 5.1 A/D Scan Mode Cycles 5.2 A/D Scan Mode Example Command/Data Table Example A/D Scan Mode Ptscb ExamplePTSPTR2 H = 1FH PTSPTR2 L = AAH Ptscount = 04H 5.3 A/D Scan Mode Example 10. Command/Data Table Example11. A/D Scan Mode Ptscb Example Serial I/O Modes Ptsvec PTS Serial I/O Mode Control Block 1 8XC196MC, MDSA1 SA0 MAJ Baud EparegSA1 SA0 † 8XC196MC, MD, MH USER’S Manual Port Address Pointer high byte PTS Serial I/O Mode Control Block 2 8XC196MC, MDPort Mask Register Rpar DataPTSCON1 Portreg PTS Serial I/O Mode Control Block8XC196MC, MD Register Location Function 8XC196MC, MD, MH USER’S Manual 13. Ssio Transmit Mode PTSCBs PTSCB1 PTSCB2 Txddone = Synchronous SIO Receive Mode Example 23. Synchronous SIO Receive Timing 14. Ssio Receive Mode PTSCBs Clrb Rxddone Standard and PTS Interrupts Rxddone = 25. Asynchronous SIO Transmit Timing 15. Asio Transmit Mode PTSCBs Standard and PTS Interrupts End-Of-PTS Interrupt Save Critical Data Is PTS Asynchronous SIO Receive Mode Example 27. Asynchronous SIO Receive Timing Portreg H = 1FH P2PIN 16. Asio Receive Mode PTSCBsSamptime = 01H Standard and PTS Interrupts End-Of-PTS Interrupt Ports Page Port Bits Type Direction Associated Peripherals I/O Ports OverviewDevice I/O Ports Standard Input-only Port Pins INPUT-ONLY Ports 1 MC, MD only Standard Input-only Port Operation Input-only Port Registers1FDAH MH P1PIN MC, MD Standard Input-only Port Considerations Bidirectional Ports 1 MH ONLY, 2, 5, and 7 MD only Bidirectional Port Pins Port Pin Special-function Associated Signals Bidirectional Port Operation Bidirectional Port Control and Status Registers Ports Bidirectional Port Structure Sfdir Bidirectional Port Pin ConfigurationsLogic Table for Bidirectional Ports in I/O Mode 8XC196MC, MD, MH USER’S Manual Port Configuration Example Bidirectional Port Pin Configuration ExampleControl Register Values for Each Configuration Bidirectional Port Considerations HZ1 P5.1/INST Ports 3 and 4 Pins Port Pins Special-functionBidirectional Ports 3 and 4 ADDRESS/DATA BUS 12. Ports 3 and 4 Control and Status Registers Bidirectional Ports 3 and 4 Address/Data Bus Operation Address/Data Bus Ports 3 and 4 Structure Using Ports 3 and 4 as I/O Design Considerations for Ports 3Standard OUTPUT-ONLY Port 13. Logic Table for Ports 3 and 4 as Open-drain I/O Configuring Output-only Port Pins 14. Standard Output-only Port PinsOutput-only Port Operation 15. Output-only Port Control Register Reset State 0000H Wgoutput Port Address1FC0H OP1 OP0 Reset State 0000H Wgoutput PortPage Serial I/O SIO Port Page SIO Block Diagram Serial I/O SIO Port Functional Overview Serial Port Control and Status Registers Serial I/O Port Signals and RegistersSerial Port Signals P1REG 1F9DH P1DIR 1F9BHP1PIN 1F9FH Serial Port Modes Synchronous Modes Modes 0 Mode Mode 0 Timing Asynchronous Modes Modes 1, 2, Serial Port Frames for Mode Mode 2 and 3 Timings Multiprocessor Communications Configuring the Serial Port Pins Programming the Serial PortProgramming the Control Register SP xCON Address 1F83H, 1F8BH = 0-1 8XC196MH Bit Function Programming the Baud Rate and Clock Source ClksrcBV7 BV9 BV8 Baudvalue = Bclk SPxBAUD Values When Using XTAL1 at 16 MHz Enabling the Serial Port Interrupts80CFH E82BH RPE/RB8 Determining Serial Port StatusRPE/RB8 TXE 8XC196MC, MD, MH USER’S Manual Frequency Generator Page Chapter Frequency Generator Port Frequency Frequency Generator SignalFrequency Generator Control and Status Registers Configuring the Output Programming the Frequency GeneratorProgramming the Frequency Freqgen Freqcnt Determining the Current Value of the Down-counterApplication Example Frequency Generator 0FAH Xmitbuf Dsb Bufsize Block of data to send Shiftreg Stb temp,freqgen0 Into freq gen Frequency Generator Page Waveform Generator Page Chapter Waveform Generator Waveform Generator Functional Overview Waveform Generator Block Diagram Waveform Generator Control and Status Registers Waveform Generator Signals and RegistersWaveform Generator Signals Waveform Generator Operation Timebase Generator Phase Driver Channels Control and Protection Circuitry Register Buffering and Synchronization Protection Circuitry Operating Modes Register Updates Event ModeOperation in Center-aligned and Edge-aligned Modes Step Center-aligned Modes Edge-aligned Modes Center-aligned Modes Center-aligned Modes Counter Operation Center-aligned Modes Output Operation Edge-Aligned Modes Edge-aligned Modes Counter Operation Programming the Waveform Generator Configuring the OutputsOutput Configuration Wgoutput Waveform Generator OP1 OP0 Sync PE7PE6 OP1 8XC196MC, MD, MH USER’S Manual Wgprotect F0HE0H 8XC196MC, MD 8XC196MH Bit Function Number Mnemonic Specifying the Carrier Period and Duty Cycle WgreloadReload 150 Reload Wgcomp Address 1FC2H,1FC4H,1FC6H Wgcounter = Wgreload WgcontrolDT7 DT6 DT5 DT4 DT9 DT8 DT3 DT2 DT1 DT0 Determining the Waveform GENERATOR’S Status Enabling the Waveform Generator InterruptsWgcounter Xxxxh Design Considerations Dead Time and Duty CycleWgcount WGCOUNT= Wgcomp Programming Example Ph3 Dsw P6.4,5 config Waveform Generator Temp1,WGOUTPUT0 Now store it Ret Demo board PI interrupt Page Pulse-width Modulator Page Chapter PULSE-WIDTH Modulator PWM Functional Overview PWM Signals and Registers PWM Signals PEx Pin Output PWM OperationPWM Control and Status Registers FFH Programming the Frequency and PeriodE6H PWM Output Frequencies Fpwm Pwmperiod Programming the Duty Cycle Pwmperiod + PWM xCONTROL Address 10-3 Sample CalculationsReading the Current Value of the Down-counter PWM Output Alternate Port Function PWM Output Enabled When Enabling the PWM OutputsPWM Output Alternate Functions Pwmcount Waveform Generator Output Configuration Wgoutput Register D/A Buffer Block Diagram Generating Analog Outputs Event Processor Array EPA Page EPA Functional Overview EPA ChannelsDevice Capture/Compare Channels Compare-only Channels COMP30 EPA and TIMER/COUNTER Signals and Registers EPA and Timer/Counter Signals EPA Control and Status Registers P0PIN 1FA8H P1PIN 1FA9H TIMER/COUNTER Functional Overview TIMER1 1F7AHTIMER2 1F7EH T1RELOAD EPA Timer/Counters Cascade Mode Timer 2 Only Quadrature Clocking Modes State of Xinternal State of Yinternal Count Direction T1DIR Quadrature Mode Timing and Count EPA Channel Functional Overview Operating in Capture Mode A Single EPA Capture/Compare Channel EPA Simplified Input-capture Structure Action Taken When a Valid Edge Occurs Overwrite Bit Status Action Taken When a Valid Edge OccursEPA Overruns EPAxCON.0 Generating a Low-speed PWM Output Operating in Compare ModePreventing EPA Overruns Generating the Highest-speed PWM Output Programming the Timers Programming the EPA and TIMER/COUNTERSConfiguring the EPA and Timer/Counter Signals Clock Source Direction Source Prescaler Divisor Resolution †T1CONTROL Prescaler Resolution † T2CONTROL Programming the Capture/Compare Channels Example EPA Control Register Settings for Channels 1, 3, orMode WGR ROT ON/RT Capture Mode Event Compare Mode ActionEPAxCON = 0-1 8XC196MH x = 0-3 8XC196MC x = 0-5 8XC196MD = 0, 2 = 1, 3 EPA xCON Address = 0, 2For EPA capture/compare channels 0, 2 For EPA capture/compare channels 1, 3 Capture Mode on Compare Mode RT = 0-3 8XC196MC, MH = 0-5 8XC196MD Reset State 00H Programming the Compare-only ChannelsComp xCON Address WGR ROT Enabling the EPA Interrupts Determining Event Status Analog-to-digital Converter PageNum-38 12.1 A/D Converter Functional Overview Angnd 12.2 A/D Converter Signals and Registers A/D Converter PinsPort Pin Signal Description A/D Control and Status Registers 12.3 A/D Converter Operation P1PIN MC,MD Programming the A/D Converter OFF1 OFF0 Programming the A/D Test RegisterAdtest Programming the A/D Time Register Adresult Write Programming the A/D Command Register Adtime Adcommand M1 M0 ModeEnabling the A/D Interrupt ACH3 ACH2 ACH1 ACH0 ADRLT90 Determining A/D Status and Conversion ResultsAdresult Read Designing External Interface Circuitry Idealized A/D Sampling Circuitry Minimizing the Effect of High Input Source Resistance Suggested A/D Input Circuit Understanding A/D Conversion Errors Using Mixed Analog and Digital Inputs 12-14 Ideal A/D Conversion Characteristic 10. Actual and Ideal A/D Conversion Characteristics 12-17 11. Terminal-based A/D Conversion Characteristic Minimum Hardware Considerations Page Minimum Connections Minimum Required SignalsRESET# I/O Port Configuration Guide Port Where to Find Configuration InformationUnused Inputs 13.1.2 I/O Port Pin Connections Minimum Hardware Connections Applying and Removing Power Noise Protection Tips ON-CHIP Oscillator Circuitry On-chip Oscillator Circuit External Crystal Connections Using AN External Clock Source External Clock Connections Resetting the Device Reset Timing Sequence Gencon Rsts DR0Rsts DRO Generating an External Reset Internal Reset Circuitry 10. Minimum Reset Circuit Issuing the Reset RST Instruction Enabling the Watchdog TimerIssuing an Illegal Idlpd Key Operand Generating Wait States Selecting the Watchdog Reset Interval 8XC196MH only First Byte Second Byte Reset Interval1EH E1H 1EH A1HPage Special Operating Modes Page Special Operating Mode Signals and Registers Operating Mode Control SignalsPort Pin Signal Type Description Clkout Operating Mode Control and Status Registers Port Pin Signal Type Description NameONCE# CCR0 Reducing Power Consumption P1MODEMHP7MODEMD 1FD1H P1REG MH 1F9DH Idle Mode Clock Control During Power-saving Modes Powerdown Mode Enabling and Disabling Powerdown Mode Entering Powerdown Mode Exiting Powerdown ModeGenerating a Hardware Reset Driving the VPP Pin Low Asserting the External Interrupt Signal External RC Circuit Selecting R1 and C1 Typical Voltage on the VPP Pin While Exiting Powerdown Once Mode Reserved Test Modes Page Interfacing with External Memory Page External Memory Interface Signals and Registers External Memory Interface SignalsSignal Port Pin Type Description Name ADV# Bytes Accessed BHE# AD0CCR0.1 CCR1.2 Buswidth WR# Signal Port PinEA# External Memory Interface Registers WRH#WRL# Register Address Description Mnemonic BHE#/WRH# † Chip Configuration Registers and Chip Configuration BytesP5REG = 11XX Xxxxb 15-6 CCR0 LOC1 LOC0 IRC1 IRC0 ALE BW0LOC1 LOC0 IRC2 IRC1 IRC0 BW1 BW0 CCR0ALE WDE CCR1WDE BW1 IRC2 BUS Width and Multiplexing CCR1 Multiplexing and Bus Width Options Buswidth Timing Diagram 8XC196MC, MD Timing Requirements for Buswidth Buswidth Signal Timing DefinitionsSymbol Definition 15.3.2 16-bit Bus Timings Timings for 16-bit Buses 15.3.3 8-bit Bus Timings Wait States Ready Control Timings for 8-bit Buses 15-18 Ready Timing Diagram One Wait State 8XC196MC, MD Address Valid to Ready Setup Bus-control Modes Bus-control Mode Bus-control Signals CCR0.3 CCR0.2BUS-CONTROL Modes Standard Bus-control Mode BHE# WR# AD0 CS# ALE OE# WE# RD# WR# OE# WE# RD# WR# Buswidth CS#Eprom RAM Write Strobe Mode 14. Write Strobe Mode 15 -bit System with Writes to Byte-wide RAMs OE# OE# WE# RD# WRH# WRL# Address Valid Strobe Mode 16. Address Valid Strobe Mode 18 -bit System with Flash Eprom OE# RD# Address Valid with Write Strobe Mode 20. Timings of Address Valid with Write Strobe Mode System BUS AC Timing Specifications VCC BuswidthWRH# WRL# CS# WE# CS# 22. System Bus Timing Explanation of AC Symbols AC Timing Symbol Definitions SignalsExternal Memory Systems Must Meet These Specifications AC Timing Definitions Microcontroller Meets These Specifications Address Setup to ALE/ADV# Low 15-35 Page Programming Nonvolatile Memory Page Programming the Nonvolatile Memory Programming Methods Otprom Memory MAP Security Features Controlling Access to Internal MemoryC196Mx Otprom Memory Map Address Range Description Hex Controlling Access to the Otprom During Normal Operation Memory Protection for Normal Operating ModeControlling Access to the Otprom During Programming Modes Read Protect Write Protect Protection Status Pccb CCB Memory Protection Options for Programming ModesSecurity Key Controlling Fetches from External Memory To set this bit Write this value To this location Uprom Programming Values and Locations for Slave ModeUsfr Programming Pulse Width PpwvaluePPW BitBitFunction Number Mnemonic Modified QUICK-PULSE Algorithm Example Ppwvalue Calculations8XC196MC, MD 8XC196MH Two 250-µs pulses required Ppwvalue = Modified Quick-pulse Algorithm Programming Mode Pins Special Program Port Pin PROG# AINC#Cpver PACT# Pmode Values Selecting the Programming ModeEntering Programming Modes Power-down Sequence Power-up and Power-down SequencesPower-up Sequence Slave Programming Mode Reading the Signature Word and Programming Voltages Slave Programming Circuit and Memory Map Device Signature Word and Programming VoltagesDevice Signature Word Programming VCC Location Value Description Address Comments Slave Programming Mode Memory MapOperating Environment Bit Mnemonic Function CCR1, CCR0LOC1 LOC0 IRC1 IRC0 WDE BW1 IRC2 Slave Programming Routines Address/Command Decoding Routine Program Word Routine Program Word Waveform 10. Dump Word Routine MnemonicDescription Timing Mnemonics10. Timing Mnemonics Mnemonic Description Auto Programming ModeAuto Programming Circuit and Memory Map 12. Auto Programming Circuit Address Internal Address Using Output from Address Internal Address UsingAuto Programming Routine 11 XC196MC/MD Auto Programming Memory Map 13. Auto Programming Routine Auto Programming Procedure ROM-dump Mode Pccb and Uprom Programming 8XC196MH only 14. Pccb and Uprom Programming Circuit Pins Pccb Programming Uprom Programming RUN-TIME Programming13. Pccb and Uprom Programming Values PMODE30 0DH 15. Run-time Programming Code Example Page Instruction Set Reference Page Appendix a Instruction SET Reference Table A-1. Opcode Map Left Half Opcode Table A-1. Opcode Map Right Half Instruction Quotient Stored Flag Set if Quotient is Table A-2. Processor Status Word PSW FlagsValue of Bits Shifted Off Instruction Jumps to Destination if Continues if Table A-4. PSW Flag Setting SymbolsSymbol Description Table A-5. Operand Variables Variable Description PSW Flag Settings Table A-6. Instruction SetMnemonic Operation C V VT ST Andb Instruction FormatDest ← Dest and SRC PTRS, Cntreg Count Count ← Cntreg Loop Srcptr ← Ptrs Dstptr Dstptr ← Srcptr Ptrs ← Srcptr +Count ← Count Dest Clear BYTE. Clears the value Mnemonic Operation Instruction Format ← Dest MOD SRC Dest MOD SRC Djnz Decrement and Jump if not Zero Djnzw Decrement and Jump if not Zero Dpts Disable Peripheral Transaction Epts Enable Peripheral TransactionEpts EXT SIGN-EXTEND Integer Into Long Extb SIGN-EXTEND SHORT-INTEGER Into Increment BYTE. Increments the value Byte operand by JGE Jump if Signed Greater than or JLE Jump if Signed Less than or Equal Negative flag is set, this instruction adds JNV Jump if Overflow Flag is Clear Jnvt Jump if OVERFLOW-TRAP Flag is JVT Jump if OVERFLOW-TRAP Flag is SET Load Byte SIGN-EXTENDED. Sign MUL Mulb Mulu Mulub Integer operand SRC, Dest Dest ← not Dest Dest ← Dest or SRC INTMASK1/WSR ← SP PSW/INTMASK ← SP SP ← PSW/INTMASK PSW/INTMASK ← SP ← INTMASK1/WSR INTMASK1 ← Scall Wreg, #count SHR Range of 0 to 31 1FH, inclusive. If Shral Arithmetic Right Shift Double Shrl Logical Right Shift DOUBLE-WORD Skip Rightmost operand SUB Subb Subc Subtract Words with Borrow DEST, SRCSubc Subcb Subtract Bytes with Borrow DEST, SRC Tijmp TBASE, INDEX, #MASK Index and #MASK = Offset× Offset + Tbase = Dest XOR Dest ← Dest XOR SRC Table A-7. Instruction Opcodes Hex Code Instruction MnemonicClrb Notb Negb Decb Extb Incb Shrb Shlb Shrab Hex Code Hex Code 8XC196MC, MD, MH USER’S Manual Dpts Epts EF Lcall DIV/DIVB/MUL/MULB Note Subc Subcb Table A-8. Instruction Lengths and Hexadecimal OpcodesArithmetic Group Direct Immediate Indirect Indexed Mnemonic Logical Direct Immediate Indirect Stack Direct Immediate Indirect Indexed Mnemonic Opcode LengthData Direct Jump Direct Conditional Jump Direct Immediate Call Direct Immediate Indirect Indexed MnemonicLength Opcode Shift Mnemonic Direct Immediate Indirect Indexed Special Mnemonic Direct Immediate IndirectPTS Mnemonic Direct Immediate Indirect Table A-9. Instruction Execution Times in State Times Arithmetic Group IndirectNormal Autoinc Short Long Reg Mem Mem Reg Logical Mnemonic Direct Immed Normal Autoinc Short Long Reg MemDIV Divb Divu Divub Reg Mem Stack Register IndirectNormal Autoinc Short Autoinc Short Long Reg LDB Ldbse Ldbze STB XCH XchbAutoinc Short Long Ljmp Sjmp Tijmp Conditional Jump Mnemonic Call Memory Indirect Indexed Mnemonic DirectNormal Autoinc Short Long Shift Mnemonic Direct Indirect IndexedClrc Clrvt Idlpd NOP RST Setc SkipPage Signal Descriptions Page Signal Name Changes Functional Groupings of SignalsTable B-1. Signal Name Changes New Name Table B-2 XC196MC Signals Arranged by Functional Categories Figure B-1 XC196MC 64-lead Shrink DIP Sdip Package U8XC196MC Figure B-2 XC196MC 84-lead Plcc Package X8XC196MC Figure B-3 XC196MC 80-lead Shrink EIAJ/QFP Package Table B-3 XC196MD Signals Arranged by Functional Categories P7.7/FREQOUT Figure B-4 XC196MD 84-lead Plcc Package X8XC196MD Figure B-5 XC196MD 80-lead Shrink EIAJ/QFP Package P2.7/SCLK1#/BCLK1 Table B-4 XC196MH Signals Arranged by Functional CategoriesEA# Extint NMI ONCE# RESET# XTAL1 XTAL2 Figure B-6 XC196MH 64-lead Shrink DIP Sdip Package X8XC196MH Figure B-7 XC196MH 84-lead Plcc Package Signal Descriptions Figure B-8 XC196MH 80-lead Shrink EIAJ/QFP Package Column Heading Description Name Table B-6. Signal DescriptionsTable B-5. Description of Columns of Table B-6 BCLK10 COMP1/P2.5/PACT#, COMP2/P2.6/CPVER, COMP3/P2.7MC, MD CCR0.1 CCR1.2Buswidth Command that invoked the power-saving mode System using a clip-on emulator P5.7/BUSWIDTH PMODE.30 Slave programmingAuto programming Programming Start SCLK10# Shift Clock 0 MH only Default Conditions Table B-7. Definition of Status Symbols Table B-8 XC196MC and MD Default Signal ConditionsPort Signals Alternate During Upon RESET# Functions RESET# Active NMI WK0 RESET# WG2 WK1WG3 WK1 PWM0 WK0 Table B-9 XC196MH Default Signal Conditions RESET#Port Signals Alternate During Upon Osc output Registers Page 8XC196MC, MH, x = Table C-1. Modules and Related RegistersCPU Table C-2. Register Name, Address, and Reset Status Xxxx EPA2TIME MC, MD Xxxx EPA3TIME MC, MDXxxx EPA4TIME MD Xxxx EPA5TIME MD P7PIN MD Xxxx P1REG MH1FFD P5REG MC, MD Xxxx TIMER1 TIMER2Usfr MC, MD Usfr MH Xxxx Watchdog Adcommand Adresult Read Adresult Write Adtest Adtime CCR0 ALE CCR1 IRC2 IRC1 IRC0 COMPxCON Comp xCON Address Table C-3 = 0-3 8XC196MC, MH For EPA capture/compare channels 0, 2 Table C-3. COMPxTIME Addresses and Reset Values Register Address Reset ValueCOMPxTIME Comp xTIME Address EPAxCON EPAxCON Address Table C-4 = 0-1 8XC196MH = 0-3 8XC196MC x = 0-5 8XC196MD Table C-4. EPAxCON Addresses and Reset Values = 0-3 8XC196MC = 0-5 8XC196MD Table C-5. EPAxTIME Addresses and Reset Values EPA Timer ValueEPAxTIME EPAxTIME = 0-1 8XC196MH x = 0-3 8XC196MC x = 0-5 8XC196MD Freqcnt Freqgen Gencon Intmask OVRTM† INTMASK1 Intpend INTPEND1 Onesreg OnesregFfffh One Table C-6. PxDIR Addresses and Reset Values PxDIR= 1 MH = 2, 5 M Table C-7. PxMODE Addresses and Reset Values PxMODE= 1 MH = 2, 5 Mx PIN7 PIN6 PIN5 PIN4 Table C-8. Special-function Signals for Ports 1, 2, 5 Pin Special-function SignalPort 8XC196MC, MD Table C-9. PxPIN Addresses and Reset Values PxPIN Table C-10. PxREG Addresses and Reset Values PxREGPxREG = 2-5 8XC196MC = 2-5, 7 8XC196MD x = 1-5 8XC196MH = 2-5 M Pimask Pimask Pipend Pipend PPW PPW150 Ppwvalue PSE PSWPSW PSW Ptssel Ptssrv Pwmcount Pwmperiod PWMxCONTROL PWM xCONTROL Address 1FB0H, 1FB2H 8XC196MH Data Received Bit SBUFxRXSBUFxRX Address 1F80H, 1F88H = 0-1 8XC196MH 8XC196MH Data to Transmit Bit SBUFxTXSbuf xTX Address 1F82H, 1F8AH = 0-1 8XC196MH Stack Pointer 150 Stack Pointer SPxBAUD SPxCON SPxCON Address 1F83H, 1F8BH = 0-1 8XC196MH SPxSTATUS T1CONTROL T1RELOAD Timer 1 Reload ValueT1RELOAD T2CONTROL 1F7EH TIMERxTimer Address 1F7AH Usfr 0AH WatchdogWatchdog WGCOMPx Wgcontrol Wgcounter Wgoutput Port Wgoutput Waveform Generator Wgoutput Waveform Generator Table C-11. Output Configuration Output Values Output Polarities WG x# Wgprotect Wgreload WSR Byte WindowsRegister Mnemonic 00E0-00FFH 00C0-00FFH 00E0-00FFH 00C0-00FFH 0080-00FFH Location T2CONTROL 1F7CH 7BH 00FCH 3DH 1EH TIMER1 † 1F7AH 00FAH 1EH 00FAH TIMER2 † 1F7EH 7BH 00FEH 3DH WGCOMP1 1FC2HPWM0CONTROL 1FB0H 7DH PWM1CONTROL 1FB2H 7DH Zero ZeroregZeroreg Page Glossary Page Glossary Characteristic DOUBLE-WORD LONG-INTEGER LSB Otprom PTS PWM SFR Special interrupt WDT Page Index Page Index Index-2 Index-3 Index-4 Index-5 Index-6 Index-7 Index-8 Index-9 Index-10 Index-11 Index-12 Index-13 Index-14