Intel 8XC196MD, 8XC196MH, 8XC196MC manual Command that invoked the power-saving mode

8XC196MC, MD, MH USER’S MANUAL

		Table B-6. Signal Descriptions (Continued)
Name	Type	Description
EPA3:0 (MC)	I/O	Event Processor Array (EPA) Capture/Compare Channels
EPA5:0 (MD)		High-speed input/output signals for the EPA capture/compare channels.
EPA1:0 (MH)		EPA5:0 are multiplexed as follows: EPA0/P2.0/PVER, EPA1/P2.1/PALE# (MC,
		MD), EPA1/P2.2/PROG# (MH), EPA2/P2.2/PROG#, EPA3/P2.3, EPA4/P7.0,
		and EPA5/P7.1.
		EPA5:4 are not implemented on the 8XC196MC and EPA5:2 are not
		implemented on the 8XC196MH.
EXTINT	I	External Interrupt
		This programmable interrupt is controlled by the WG_PROTECT register. This
		register controls whether the interrupt is edge triggered or sampled and whether
		a rising edge/high level or falling edge/low level activates the interrupt.
		In powerdown mode, asserting the EXTINT signal for at least 50 ns causes the
		device to resume normal operation. The interrupt need not be enabled. If the
		EXTINT interrupt is enabled, the CPU executes the interrupt service routine.
		Otherwise, the CPU executes the instruction that immediately follows the
		command that invoked the power-saving mode.
		In idle mode, asserting any enabled interrupt causes the device to resume
		normal operation.
FREQOUT	O	Frequency Generator Output
(MD only)		A fixed 50% duty cycle waveform that can vary in frequency from 4 KHz to 1
		MHz (assuming FXTAL1 = 16 MHz).
		FREQOUT is multiplexed with P7.7.
		FREQOUT is not implemented on the 8XC196MC or MH.
INST	O	Instruction Fetch
		This active-high output signal is valid only during external memory bus cycles.
		When high, INST indicates that an instruction is being fetched from external
		memory. The signal remains high during the entire bus cycle of an external
		instruction fetch. INST is low for data accesses, including interrupt vector
		fetches and chip configuration byte reads. INST is low during internal memory
		fetches.
		INST is multiplexed with P5.1.
NMI	I	Nonmaskable Interrupt
		In normal operating mode, a rising edge on NMI generates a nonmaskable
		interrupt. NMI has the highest priority of all prioritized interrupts. Assert NMI for
		greater than one state time to guarantee that it is recognized.

B-16