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Intel 8XC196MD, 8XC196MH, 8XC196MC manual Command that invoked the power-saving mode

Models: 8XC196MD 8XC196MH 8XC196MC

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8XC196MC, MD, MH USER’S MANUAL

		Table B-6. Signal Descriptions (Continued)
Name	Type	Description

EPA3:0 (MC)	I/O	Event Processor Array (EPA) Capture/Compare Channels
EPA5:0 (MD)		High-speed input/output signals for the EPA capture/compare channels.
EPA1:0 (MH)		EPA5:0 are multiplexed as follows: EPA0/P2.0/PVER, EPA1/P2.1/PALE# (MC,
		MD), EPA1/P2.2/PROG# (MH), EPA2/P2.2/PROG#, EPA3/P2.3, EPA4/P7.0,
		and EPA5/P7.1.
		EPA5:4 are not implemented on the 8XC196MC and EPA5:2 are not
		implemented on the 8XC196MH.
EXTINT	I	External Interrupt
		This programmable interrupt is controlled by the WG_PROTECT register. This
		register controls whether the interrupt is edge triggered or sampled and whether
		a rising edge/high level or falling edge/low level activates the interrupt.
		In powerdown mode, asserting the EXTINT signal for at least 50 ns causes the
		device to resume normal operation. The interrupt need not be enabled. If the
		EXTINT interrupt is enabled, the CPU executes the interrupt service routine.
		Otherwise, the CPU executes the instruction that immediately follows the
		command that invoked the power-saving mode.
		In idle mode, asserting any enabled interrupt causes the device to resume
		normal operation.
FREQOUT	O	Frequency Generator Output
(MD only)		A fixed 50% duty cycle waveform that can vary in frequency from 4 KHz to 1

		MHz (assuming FXTAL1 = 16 MHz).
		FREQOUT is multiplexed with P7.7.
		FREQOUT is not implemented on the 8XC196MC or MH.
INST	O	Instruction Fetch
		This active-high output signal is valid only during external memory bus cycles.
		When high, INST indicates that an instruction is being fetched from external
		memory. The signal remains high during the entire bus cycle of an external
		instruction fetch. INST is low for data accesses, including interrupt vector
		fetches and chip configuration byte reads. INST is low during internal memory
		fetches.
		INST is multiplexed with P5.1.
NMI	I	Nonmaskable Interrupt
		In normal operating mode, a rising edge on NMI generates a nonmaskable
		interrupt. NMI has the highest priority of all prioritized interrupts. Assert NMI for
		greater than one state time to guarantee that it is recognized.

B-16

Image 465

Intel 8XC196MD, 8XC196MH, 8XC196MC manual Command that invoked the power-saving mode

Contents

8XC196MC, 8XC196MD, 8XC196MH Microcontroller User’ Manual We Value Your Opinion Page 8XC196MC, 8XC196MD, 8XC196MH Microcontroller User’s Manual Intel Corporation Contents Chapter Memory Partitions Contents 8XC196MC, MD, MH USER’S Manual Functional Overview Programming the Frequency Generator PWM Signals and RegistersApplication Example Programming the Waveform GeneratorChapter Event Processor Array EPA Chapter Minimum Hardware Considerations Chapter Programming the Nonvolatile Memory Appendix C Registers Glossary Index Figures 10-5 15-9 Ready Timing Diagram One Wait State 8XC196MH 15-21 Tables 11-12 16-7 Pmode Values Guide to This Manual Page Chapter Guide to this Manual Manual ContentsSpecial Operating Modes Assert and deassert Notational Conventions and TerminologyNumbers Related Documents Handbooks and Product Information Application Notes, Application Briefs, and Article ReprintsTitle Order Number MCS 96 Microcontroller Datasheets Automotive MCS 96 Microcontroller Datasheets Commercial/ExpressThis Page Left Intentionally Blank Guide to this Manual This Page Left Intentionally Blank World Wide Web Technical SupportProduct Literature Page Architectural Overview Page Typical Applications Microcontroller FeaturesFunctional Overview Features of the 8XC196Mx Product FamilyOtprom SIO PWMPTS EPA PWM WDT SIO ROMCPU RAMCPU Control Register FileRegister Arithmetic-logic Unit Ralu Instruction Format Code ExecutionMemory Interface Unit Interrupt ServiceClock Circuitry Internal TimingState Times at Various Frequencies Internal PeripheralsSerial I/O SIO Port 1 I/O PortsPulse-width Modulator PWM Event Processor Array EPA and Timer/CountersFrequency Generator Waveform GeneratorReducing Power Consumption Watchdog TimerTesting the Printed Circuit Board Analog-to-digital ConverterProgramming the Nonvolatile Memory Programming Considerations Page Operand Type Definitions Overview of the Instruction SETOperand Type No. Signed Possible Values Addressing RestrictionsByte Operands BIT OperandsSHORT-INTEGER Operands Word OperandsDOUBLE-WORD Operands Integer OperandsConverting Operands LONG-INTEGER OperandsConditional Jumps Floating Point OperationsAddressing Modes Immediate Addressing Direct AddressingIndirect Addressing Definition of Temporary RegistersIndirect Addressing with Autoincrement Indexed AddressingIndirect Addressing with the Stack Pointer Short-indexed AddressingZero-indexed Addressing Long-indexed AddressingAssembly Language Addressing Mode Selections Using RegistersSoftware Standards and Conventions Linking Subroutines Addressing 32-bit OperandsSoftware Protection Features and Guidelines 8XC196MC, MD, MH USER’S Manual Memory Partitions Page Memory Partitions External Devices Memory or I/OProgram and Special-purpose Memory Memory Map Program MemoryDevice Description Addressing ModesSpecial-purpose Memory Addresses Special-purpose MemoryReserved Memory Locations Interrupt and PTS VectorsChip Configuration Bytes CCBs Special-function Registers SFRsSecurity Key Peripheral SFRs Memory-mapped SFRsPeripheral SFRs 8XC196MC EPA and Timer SFRsPort 2 SFRs SFRsPorts 2 and 7 SFRs Peripheral SFRs 8XC196MDPort 0 and 2 SFRs Peripheral SFRs 8XC196MHPort 1 SFRs Serial I/O Port SFRsAddress Register File Memory MapGeneral-purpose Register RAM Register File Memory AddressesStack Pointer SP Device and Hex Address Range Description Addressing ModesCPU Special-function Registers SFRs CPU SFRsAddress High Odd Byte Low Even Byte 8XC196MC,MD Windowing02FFH 01FFH 00FFHWSR Selecting a WindowBit Function Number WSR Value for Peripherals10. Selecting a Window of the Upper Register File Addressing a Location Through a Window12. Windowed Base Addresses 11. WindowsBase WSR Value WSR Value for Peripheral SFRs2.2 64-byte Windowing Example 2.1 32-byte Windowing Example2.3 128-byte Windowing Example Unsupported Locations Windowing Example?WSR Using the Linker Locator to Set Up a WindowThis listing shows the disassembled code LDB WSR, #12H Windowing and Addressing ModesPage Standard and PTS Interrupts Page Overview of Interrupts Chapter Standard and PTS InterruptsFlow Diagram for PTS and Standard Interrupts Interrupt Signals and Registers Interrupt SignalsInterrupt and PTS Control and Status Registers Pipend 1FBEH Interrupt Sources and PrioritiesPtssel PtssrvInterrupt Controller PTS Service Interrupt Sources, Vectors, and PrioritiesInterrupt Source Mnemonic Name Vector Priority External Interrupt Pin Special InterruptsUnimplemented Opcode Software TrapWaveform Generator Protection Circuitry Multiplexed Interrupt SourcesFlow Diagram for the Ovrtm Interrupt End-of-PTS Interrupts Interrupt LatencySituations that Increase Interrupt Latency Standard Interrupt Latency Calculating LatencyStandard Interrupt Response Time PTS Interrupt Latency PTS Mode Execution Time in State Times Programming the InterruptsExecution Times for PTS Cycles Standard and PTS Interrupts 8XC196MC Ptssel8XC196MD Bit FunctionCOMP2 EPA2 COMP1 EPA1 COMP3 COMP0 EPA0 Ovrtm IntmaskBit Mnemonic Interrupt Standard Vector COMP2 MC, MDNMI Extint INTMASK1NMI Extint EPA5 NMI Extint SPI COMP3 EPA3 COMP4 EPA4 RI1 RI0 TI1 TI0Pimask 8XC196MC 8XC196MDBit Function Number Mnemonic Modifying Interrupt Priorities PimaskOVRTM1 Standard and PTS Interrupts Determining the Source of an Interrupt Intpend 10. Interrupt Pending Intpend RegisterINTPEND1 11. Interrupt Pending 1 INTPEND1 RegisterPipend 12. Peripheral Interrupt Pending Pipend RegisterPipend Initializing the PTS Control BlocksSpecifying the PTS Count Ptssrv 14. PTS Service Ptssrv RegisterSelecting the PTS Mode Single Transfer ModePtscon Ptsdst H Ptsdst L Ptssrc H Ptssrc L Ptscon Ptscount PTS Single Transfer Mode Control BlockRegister Location Function Ptsdst Ptscb +Standard and PTS Interrupts Block Transfer Mode Single Transfer Mode PtscbBlock Transfer Mode Ptscb Ptsblock Ptscb + PTS Block Transfer Mode Control Block5 A/D Scan Mode PTS A/D Scan Mode Control Block Address Contents A/D Scan Mode Command/Data Table5.2 A/D Scan Mode Example 5.1 A/D Scan Mode CyclesA/D Scan Mode Ptscb Example Command/Data Table ExamplePTSPTR2 H = 1FH PTSPTR2 L = AAH Ptscount = 04H10. Command/Data Table Example 5.3 A/D Scan Mode Example11. A/D Scan Mode Ptscb Example Serial I/O ModesPTS Serial I/O Mode Control Block 1 8XC196MC, MD SA1 SA0 MAJPtsvec Epareg BaudSA1 SA0 †8XC196MC, MD, MH USER’S Manual PTS Serial I/O Mode Control Block 2 8XC196MC, MD Port Mask RegisterPort Address Pointer high byte Data PTSCON1Rpar PTS Serial I/O Mode Control Block 8XC196MC, MD Register Location FunctionPortreg 8XC196MC, MD, MH USER’S Manual PTSCB1 PTSCB2 13. Ssio Transmit Mode PTSCBsTxddone = 23. Synchronous SIO Receive Timing Synchronous SIO Receive Mode ExampleClrb Rxddone 14. Ssio Receive Mode PTSCBsStandard and PTS Interrupts Rxddone = 25. Asynchronous SIO Transmit Timing 15. Asio Transmit Mode PTSCBs Standard and PTS Interrupts End-Of-PTS Interrupt Save Critical Data Is PTS 27. Asynchronous SIO Receive Timing Asynchronous SIO Receive Mode Example16. Asio Receive Mode PTSCBs Samptime = 01HPortreg H = 1FH P2PIN Standard and PTS Interrupts End-Of-PTS Interrupt Ports Page I/O Ports Overview Device I/O PortsPort Bits Type Direction Associated Peripherals INPUT-ONLY Ports 1 MC, MD only Standard Input-only Port PinsInput-only Port Registers Standard Input-only Port Operation1FDAH MH P1PIN MC, MDBidirectional Ports 1 MH ONLY, 2, 5, and 7 MD only Standard Input-only Port ConsiderationsPort Pin Special-function Associated Signals Bidirectional Port PinsBidirectional Port Control and Status Registers Bidirectional Port OperationPorts Bidirectional Port Structure Bidirectional Port Pin Configurations Logic Table for Bidirectional Ports in I/O ModeSfdir 8XC196MC, MD, MH USER’S Manual Bidirectional Port Pin Configuration Example Control Register Values for Each ConfigurationPort Configuration Example HZ1 Bidirectional Port ConsiderationsP5.1/INST Port Pins Special-function Ports 3 and 4 PinsBidirectional Ports 3 and 4 ADDRESS/DATA BUS 12. Ports 3 and 4 Control and Status RegistersAddress/Data Bus Ports 3 and 4 Structure Bidirectional Ports 3 and 4 Address/Data Bus OperationDesign Considerations for Ports 3 Using Ports 3 and 4 as I/OStandard OUTPUT-ONLY Port 13. Logic Table for Ports 3 and 4 as Open-drain I/O14. Standard Output-only Port Pins Configuring Output-only Port PinsOutput-only Port Operation 15. Output-only Port Control RegisterWgoutput Port Address Reset State 0000H1FC0H OP1 OP0Wgoutput Port Reset State 0000HPage Serial I/O SIO Port Page Serial I/O SIO Port Functional Overview SIO Block DiagramSerial I/O Port Signals and Registers Serial Port SignalsSerial Port Control and Status Registers P1DIR 1F9BH P1PIN 1F9FHP1REG 1F9DH Serial Port Modes Mode Synchronous Modes Modes 0Mode 0 Timing Asynchronous Modes Modes 1, 2, Serial Port Frames for Mode Multiprocessor Communications Mode 2 and 3 TimingsProgramming the Serial Port Configuring the Serial Port PinsProgramming the Control Register SP xCON Address 1F83H, 1F8BH = 0-1 8XC196MHBit Function Clksrc Programming the Baud Rate and Clock SourceBV7 BV9 BV8Bclk Baudvalue =Enabling the Serial Port Interrupts SPxBAUD Values When Using XTAL1 at 16 MHz80CFH E82BHDetermining Serial Port Status RPE/RB8 TXERPE/RB8 8XC196MC, MD, MH USER’S Manual Frequency Generator Page Chapter Frequency Generator Frequency Generator Signal Frequency Generator Control and Status RegistersPort Frequency Programming the Frequency Generator Configuring the OutputProgramming the Frequency FreqgenDetermining the Current Value of the Down-counter Application ExampleFreqcnt Frequency Generator 0FAH Xmitbuf Dsb Bufsize Block of data to send Shiftreg Stb temp,freqgen0 Into freq gen Frequency Generator Page Waveform Generator Page Waveform Generator Functional Overview Chapter Waveform GeneratorWaveform Generator Block Diagram Waveform Generator Signals and Registers Waveform Generator SignalsWaveform Generator Control and Status Registers Timebase Generator Waveform Generator OperationControl and Protection Circuitry Phase Driver ChannelsProtection Circuitry Register Buffering and SynchronizationOperating Modes Event Mode Register UpdatesOperation in Center-aligned and Edge-aligned Modes Step Center-aligned Modes Edge-aligned ModesCenter-aligned Modes Counter Operation Center-aligned ModesCenter-aligned Modes Output Operation Edge-Aligned Modes Edge-aligned Modes Counter Operation Configuring the Outputs Output ConfigurationProgramming the Waveform Generator OP1 OP0 Sync PE7 Wgoutput Waveform GeneratorPE6 OP18XC196MC, MD, MH USER’S Manual F0H WgprotectE0H 8XC196MC, MD 8XC196MH Bit Function Number MnemonicWgreload Specifying the Carrier Period and Duty CycleReload 150 Reload1FC2H,1FC4H,1FC6H Wgcomp AddressWgcontrol DT7 DT6 DT5 DT4 DT9 DT8 DT3 DT2 DT1 DT0Wgcounter = Wgreload Enabling the Waveform Generator Interrupts Determining the Waveform GENERATOR’S StatusWgcounter XxxxhDead Time and Duty Cycle Design ConsiderationsWgcount WGCOUNT= WgcompProgramming Example Ph3 Dsw P6.4,5 config Waveform Generator Temp1,WGOUTPUT0 Now store it Ret Demo board PI interrupt Page Pulse-width Modulator Page PWM Functional Overview Chapter PULSE-WIDTH ModulatorPWM Signals PWM Signals and RegistersPWM Operation PWM Control and Status RegistersPEx Pin Output Programming the Frequency and Period E6HFFH Pwmperiod PWM Output Frequencies FpwmPwmperiod + Programming the Duty CycleSample Calculations Reading the Current Value of the Down-counterPWM xCONTROL Address 10-3 Enabling the PWM Outputs PWM Output Alternate Port Function PWM Output Enabled WhenPWM Output Alternate Functions PwmcountWaveform Generator Output Configuration Wgoutput Register Generating Analog Outputs D/A Buffer Block DiagramEvent Processor Array EPA Page EPA Channels EPA Functional OverviewDevice Capture/Compare Channels Compare-only Channels COMP30EPA and Timer/Counter Signals EPA and TIMER/COUNTER Signals and RegistersEPA Control and Status Registers P1PIN 1FA9H P0PIN 1FA8HTIMER1 1F7AH TIMER/COUNTER Functional OverviewTIMER2 1F7EH T1RELOADEPA Timer/Counters Quadrature Clocking Modes Cascade Mode Timer 2 OnlyT1DIR State of Xinternal State of Yinternal Count DirectionEPA Channel Functional Overview Quadrature Mode Timing and CountA Single EPA Capture/Compare Channel Operating in Capture ModeEPA Simplified Input-capture Structure Overwrite Bit Status Action Taken When a Valid Edge Occurs Action Taken When a Valid Edge OccursEPA Overruns EPAxCON.0Operating in Compare Mode Preventing EPA OverrunsGenerating a Low-speed PWM Output Generating the Highest-speed PWM Output Programming the EPA and TIMER/COUNTERS Configuring the EPA and Timer/Counter SignalsProgramming the Timers Prescaler Divisor Resolution † T1CONTROLClock Source Direction Source T2CONTROL Prescaler Resolution †Example EPA Control Register Settings for Channels 1, 3, or Mode WGR ROT ON/RTProgramming the Capture/Compare Channels Compare Mode Action Capture Mode EventEPAxCON = 0-1 8XC196MH x = 0-3 8XC196MC x = 0-5 8XC196MD = 0, 2 = 1, 3= 0, 2 EPA xCON AddressFor EPA capture/compare channels 0, 2 For EPA capture/compare channels 1, 3Compare Mode RT Capture Mode onProgramming the Compare-only Channels = 0-3 8XC196MC, MH = 0-5 8XC196MD Reset State 00HComp xCON Address WGR ROTEnabling the EPA Interrupts Determining Event Status Analog-to-digital Converter PageNum-38 Angnd 12.1 A/D Converter Functional OverviewA/D Converter Pins 12.2 A/D Converter Signals and RegistersPort Pin Signal Description A/D Control and Status RegistersP1PIN MC,MD 12.3 A/D Converter OperationProgramming the A/D Converter Programming the A/D Test Register AdtestOFF1 OFF0 Adresult Write Programming the A/D Time RegisterAdtime Programming the A/D Command RegisterM1 M0 Mode AdcommandEnabling the A/D Interrupt ACH3 ACH2 ACH1 ACH0Determining A/D Status and Conversion Results Adresult ReadADRLT90 Idealized A/D Sampling Circuitry Designing External Interface CircuitryMinimizing the Effect of High Input Source Resistance Suggested A/D Input Circuit Using Mixed Analog and Digital Inputs Understanding A/D Conversion Errors12-14 Ideal A/D Conversion Characteristic 10. Actual and Ideal A/D Conversion Characteristics 12-17 11. Terminal-based A/D Conversion Characteristic Minimum Hardware Considerations Page Minimum Required Signals RESET#Minimum Connections Port Where to Find Configuration Information I/O Port Configuration GuideUnused Inputs 13.1.2 I/O Port Pin ConnectionsMinimum Hardware Connections Noise Protection Tips Applying and Removing PowerOn-chip Oscillator Circuit ON-CHIP Oscillator CircuitryExternal Crystal Connections External Clock Connections Using AN External Clock SourceReset Timing Sequence Resetting the DeviceRsts DR0 GenconRsts DROInternal Reset Circuitry Generating an External Reset10. Minimum Reset Circuit Enabling the Watchdog Timer Issuing the Reset RST InstructionIssuing an Illegal Idlpd Key Operand Generating Wait StatesFirst Byte Second Byte Reset Interval Selecting the Watchdog Reset Interval 8XC196MH only1EH E1H 1EH A1HPage Special Operating Modes Page Operating Mode Control Signals Special Operating Mode Signals and RegistersPort Pin Signal Type Description ClkoutPort Pin Signal Type Description Name Operating Mode Control and Status RegistersONCE# CCR0P1MODEMH Reducing Power ConsumptionP7MODEMD 1FD1H P1REG MH 1F9DHClock Control During Power-saving Modes Idle ModeEnabling and Disabling Powerdown Mode Powerdown ModeExiting Powerdown Mode Entering Powerdown ModeGenerating a Hardware Reset Driving the VPP Pin LowAsserting the External Interrupt Signal Selecting R1 and C1 External RC CircuitTypical Voltage on the VPP Pin While Exiting Powerdown Once Mode Reserved Test Modes Page Interfacing with External Memory Page External Memory Interface Signals External Memory Interface Signals and RegistersSignal Port Pin Type Description Name ADV#BHE# AD0 Bytes AccessedCCR0.1 CCR1.2 BuswidthSignal Port Pin EA#WR# WRH# External Memory Interface RegistersWRL# Register Address Description MnemonicChip Configuration Registers and Chip Configuration Bytes P5REG = 11XX XxxxbBHE#/WRH# † 15-6 LOC1 LOC0 IRC1 IRC0 ALE BW0 CCR0LOC1 LOC0 IRC2 IRC1 IRC0CCR0 ALEBW1 BW0 CCR1 WDE BW1 IRC2WDE CCR1 BUS Width and MultiplexingMultiplexing and Bus Width Options Buswidth Timing Diagram 8XC196MC, MD Buswidth Signal Timing Definitions Symbol DefinitionTiming Requirements for Buswidth 15.3.2 16-bit Bus Timings Timings for 16-bit Buses 15.3.3 8-bit Bus Timings Timings for 8-bit Buses Wait States Ready Control15-18 Ready Timing Diagram One Wait State 8XC196MC, MD Address Valid to Ready Setup Bus-control Mode Bus-control Signals CCR0.3 CCR0.2 BUS-CONTROL ModesBus-control Modes BHE# WR# AD0 Standard Bus-control ModeALE OE# WE# RD# WR# CS#Buswidth CS# Eprom RAMOE# WE# RD# WR# 14. Write Strobe Mode Write Strobe ModeOE# OE# WE# RD# WRH# WRL# 15 -bit System with Writes to Byte-wide RAMs16. Address Valid Strobe Mode Address Valid Strobe Mode18 -bit System with Flash OE# RD# Eprom20. Timings of Address Valid with Write Strobe Mode Address Valid with Write Strobe ModeVCC Buswidth System BUS AC Timing SpecificationsWRH# WRL# CS# WE# CS#22. System Bus Timing AC Timing Symbol Definitions Signals Explanation of AC SymbolsExternal Memory Systems Must Meet These Specifications AC Timing DefinitionsAddress Setup to ALE/ADV# Low Microcontroller Meets These Specifications15-35 Page Programming Nonvolatile Memory Page Programming Methods Programming the Nonvolatile MemoryOtprom Memory MAP Controlling Access to Internal Memory Security FeaturesC196Mx Otprom Memory Map Address Range Description HexMemory Protection for Normal Operating Mode Controlling Access to the Otprom During Normal OperationControlling Access to the Otprom During Programming Modes Read Protect Write Protect Protection StatusMemory Protection Options for Programming Modes Security KeyPccb CCB Controlling Fetches from External Memory Uprom Programming Values and Locations for Slave Mode UsfrTo set this bit Write this value To this location Ppwvalue Programming Pulse WidthPPW BitBitFunction Number MnemonicExample Ppwvalue Calculations Modified QUICK-PULSE Algorithm8XC196MC, MD 8XC196MH Two 250-µs pulses required Ppwvalue =Modified Quick-pulse Algorithm Special Program Port Pin Programming Mode PinsAINC# PROG#Cpver PACT#Selecting the Programming Mode Entering Programming ModesPmode Values Power-up and Power-down Sequences Power-up SequencePower-down Sequence Reading the Signature Word and Programming Voltages Slave Programming ModeDevice Signature Word and Programming Voltages Slave Programming Circuit and Memory MapDevice Signature Word Programming VCC Location ValueSlave Programming Mode Memory Map Operating EnvironmentDescription Address Comments CCR1, CCR0 LOC1 LOC0 IRC1 IRC0 WDE BW1 IRC2Bit Mnemonic Function Slave Programming Routines Address/Command Decoding Routine Program Word Routine Program Word Waveform 10. Dump Word Routine Timing Mnemonics 10. Timing MnemonicsMnemonicDescription Auto Programming Mode Auto Programming Circuit and Memory MapMnemonic Description 12. Auto Programming Circuit Address Internal Address Using Address Internal Address Using Output fromAuto Programming Routine 11 XC196MC/MD Auto Programming Memory Map13. Auto Programming Routine Auto Programming Procedure Pccb and Uprom Programming 8XC196MH only ROM-dump Mode14. Pccb and Uprom Programming Circuit RUN-TIME Programming Pins Pccb Programming Uprom Programming13. Pccb and Uprom Programming Values PMODE30 0DH15. Run-time Programming Code Example Page Instruction Set Reference Page Appendix a Instruction SET Reference Opcode Table A-1. Opcode Map Left HalfTable A-1. Opcode Map Right Half Table A-2. Processor Status Word PSW Flags Value of Bits Shifted OffInstruction Quotient Stored Flag Set if Quotient is Table A-4. PSW Flag Setting Symbols Symbol DescriptionInstruction Jumps to Destination if Continues if Variable Description Table A-5. Operand VariablesTable A-6. Instruction Set PSW Flag SettingsMnemonic Operation C V VT STInstruction Format Dest ← Dest and SRCAndb Count PTRS, CntregDstptr ← Srcptr Ptrs ← Srcptr + Count ← Cntreg Loop Srcptr ← Ptrs DstptrCount ← Count DestClear BYTE. Clears the value Mnemonic Operation Instruction Format Dest MOD SRC ← Dest MOD SRCDjnzw Decrement and Jump if not Zero Djnz Decrement and Jump if not ZeroEpts Enable Peripheral Transaction Dpts Disable Peripheral TransactionEpts EXT SIGN-EXTEND Integer Into LongExtb SIGN-EXTEND SHORT-INTEGER Into Increment BYTE. Increments the value Byte operand by JGE Jump if Signed Greater than or JLE Jump if Signed Less than or Equal Negative flag is set, this instruction adds JNV Jump if Overflow Flag is Clear Jnvt Jump if OVERFLOW-TRAP Flag is JVT Jump if OVERFLOW-TRAP Flag is SET Load Byte SIGN-EXTENDED. Sign Mulb MULMulub MuluSRC, Dest Integer operandDest ← Dest or SRC Dest ← not DestPSW/INTMASK ← SP INTMASK1/WSR ← SPSP ← INTMASK1/WSR INTMASK1 ← SP ← PSW/INTMASK PSW/INTMASK ←Scall Wreg, #count SHR Range of 0 to 31 1FH, inclusive. If Shral Arithmetic Right Shift Double Skip Shrl Logical Right Shift DOUBLE-WORDSUB Rightmost operandSubc Subtract Words with Borrow DEST, SRC SubbSubc Subcb Subtract Bytes with Borrow DEST, SRCIndex and #MASK = Offset × Offset + Tbase = DestTijmp TBASE, INDEX, #MASK Dest ← Dest XOR SRC XORHex Code Instruction Mnemonic Table A-7. Instruction OpcodesClrb Notb Negb Decb Extb Incb Shrb Shlb ShrabHex Code Hex Code 8XC196MC, MD, MH USER’S Manual EF Lcall Dpts EptsDIV/DIVB/MUL/MULB Note Table A-8. Instruction Lengths and Hexadecimal Opcodes Arithmetic Group Direct Immediate Indirect Indexed MnemonicSubc Subcb Logical Direct Immediate Indirect Opcode Length Stack Direct Immediate Indirect Indexed MnemonicData Direct Jump DirectCall Direct Immediate Indirect Indexed Mnemonic Length OpcodeConditional Jump Direct Immediate Special Mnemonic Direct Immediate Indirect Shift Mnemonic Direct Immediate Indirect IndexedPTS Mnemonic Direct Immediate IndirectArithmetic Group Indirect Table A-9. Instruction Execution Times in State TimesNormal Autoinc Short Long Reg Mem Mem RegMnemonic Direct Immed Normal Autoinc Short Long Reg Mem DIV Divb Divu DivubLogical Stack Register Indirect Normal Autoinc ShortReg Mem LDB Ldbse Ldbze STB XCH Xchb Autoinc Short Long RegAutoinc Short Long Ljmp Sjmp TijmpCall Memory Indirect Indexed Mnemonic Direct Normal Autoinc Short LongConditional Jump Mnemonic Indirect Indexed Shift Mnemonic DirectClrc Clrvt Idlpd NOP RST Setc SkipPage Signal Descriptions Page Functional Groupings of Signals Signal Name ChangesTable B-1. Signal Name Changes New NameTable B-2 XC196MC Signals Arranged by Functional Categories U8XC196MC Figure B-1 XC196MC 64-lead Shrink DIP Sdip PackageX8XC196MC Figure B-2 XC196MC 84-lead Plcc PackageFigure B-3 XC196MC 80-lead Shrink EIAJ/QFP Package P7.7/FREQOUT Table B-3 XC196MD Signals Arranged by Functional CategoriesX8XC196MD Figure B-4 XC196MD 84-lead Plcc PackageFigure B-5 XC196MD 80-lead Shrink EIAJ/QFP Package Table B-4 XC196MH Signals Arranged by Functional Categories EA# Extint NMI ONCE# RESET# XTAL1 XTAL2P2.7/SCLK1#/BCLK1 X8XC196MH Figure B-6 XC196MH 64-lead Shrink DIP Sdip PackageFigure B-7 XC196MH 84-lead Plcc Package Figure B-8 XC196MH 80-lead Shrink EIAJ/QFP Package Signal DescriptionsTable B-6. Signal Descriptions Table B-5. Description of Columns of Table B-6Column Heading Description Name BCLK10 CCR0.1 CCR1.2 BuswidthCOMP1/P2.5/PACT#, COMP2/P2.6/CPVER, COMP3/P2.7MC, MD Command that invoked the power-saving mode System using a clip-on emulator P5.7/BUSWIDTH Slave programming Auto programmingPMODE.30 Programming Start SCLK10# Shift Clock 0 MH only Default Conditions Table B-8 XC196MC and MD Default Signal Conditions Table B-7. Definition of Status SymbolsPort Signals Alternate During Upon RESET# Functions RESET# ActiveWG2 WK1 NMI WK0 RESET#WG3 WK1 PWM0 WK0RESET# Table B-9 XC196MH Default Signal ConditionsPort Signals Alternate During UponOsc output Registers Page Table C-1. Modules and Related Registers CPU8XC196MC, MH, x = Table C-2. Register Name, Address, and Reset Status Xxxx EPA3TIME MC, MD Xxxx EPA2TIME MC, MDXxxx EPA4TIME MD Xxxx EPA5TIME MDXxxx P1REG MH P7PIN MD1FFD P5REG MC, MDTIMER2 Xxxx TIMER1Usfr MC, MD Usfr MH Xxxx WatchdogAdcommand Adresult Read Adresult Write Adtest Adtime CCR0 ALE CCR1 IRC2 IRC1 IRC0 Comp xCON Address Table C-3 = 0-3 8XC196MC, MH COMPxCONFor EPA capture/compare channels 0, 2 Register Address Reset Value Table C-3. COMPxTIME Addresses and Reset ValuesCOMPxTIME Comp xTIME AddressEPAxCON = 0-3 8XC196MC x = 0-5 8XC196MD EPAxCON Address Table C-4 = 0-1 8XC196MH= 0-3 8XC196MC = 0-5 8XC196MD Table C-4. EPAxCON Addresses and Reset ValuesEPA Timer Value Table C-5. EPAxTIME Addresses and Reset ValuesEPAxTIME EPAxTIME = 0-1 8XC196MH x = 0-3 8XC196MC x = 0-5 8XC196MDFreqcnt Freqgen Gencon OVRTM† IntmaskINTMASK1 Intpend INTPEND1 Onesreg OnesregFfffh OnePxDIR Table C-6. PxDIR Addresses and Reset Values= 1 MH = 2, 5 MPxMODE Table C-7. PxMODE Addresses and Reset Values= 1 MH = 2, 5 Mx PIN7 PIN6 PIN5 PIN4Pin Special-function Signal Table C-8. Special-function Signals for Ports 1, 2, 5Port 8XC196MC, MDPxPIN Table C-9. PxPIN Addresses and Reset ValuesPxREG Table C-10. PxREG Addresses and Reset ValuesPxREG = 2-5 8XC196MC = 2-5, 7 8XC196MD x = 1-5 8XC196MH = 2-5 MPimask Pimask Pipend Pipend PPW150 Ppwvalue PPWPSW PSWPSE PSW Ptssel Ptssrv Pwmcount Pwmperiod PWM xCONTROL Address 1FB0H, 1FB2H PWMxCONTROLSBUFxRX SBUFxRX Address 1F80H, 1F88H = 0-1 8XC196MH8XC196MH Data Received Bit SBUFxTX Sbuf xTX Address 1F82H, 1F8AH = 0-1 8XC196MH8XC196MH Data to Transmit Bit 150 Stack Pointer Stack PointerSPxBAUD SPxCON Address 1F83H, 1F8BH = 0-1 8XC196MH SPxCONSPxSTATUS T1CONTROL Timer 1 Reload Value T1RELOADT1RELOAD T2CONTROL TIMERx Timer Address 1F7AH1F7EH Usfr Watchdog Watchdog0AH WGCOMPx Wgcontrol Wgcounter Wgoutput Port Wgoutput Waveform Generator Wgoutput Waveform Generator Output Values Output Polarities WG x# Table C-11. Output ConfigurationWgprotect Wgreload Byte Windows WSRRegister Mnemonic 00E0-00FFH 00C0-00FFH00E0-00FFH 00C0-00FFH 0080-00FFH Location 1EH 00FAH TIMER2 † 1F7EH 7BH 00FEH 3DH WGCOMP1 1FC2H T2CONTROL 1F7CH 7BH 00FCH 3DH 1EH TIMER1 † 1F7AH 00FAHPWM0CONTROL 1FB0H 7DH PWM1CONTROL 1FB2H 7DHZeroreg ZeroregZero Page Glossary Page Glossary Characteristic DOUBLE-WORD LONG-INTEGER LSB Otprom PTS PWM SFR Special interrupt WDT Page Index Page Index Index-2 Index-3 Index-4 Index-5 Index-6 Index-7 Index-8 Index-9 Index-10 Index-11 Index-12 Index-13 Index-14