Intel 8XC196MD, 8XC196MH, 8XC196MC manual Integer Operands, DOUBLE-WORD Operands

PROGRAMMING CONSIDERATIONS

WORDs must be aligned at even byte boundaries in the address space. The least-significant byte of the WORD is in the even byte address, and the most-significant byte is in the next higher (odd) address. The address of a WORD is that of its least-significant byte (the even byte address). WORD operations to odd addresses are not guaranteed to operate in a consistent manner.

3.1.5INTEGER Operands

An INTEGER is a 16-bit, signed variable that can take on values from –32,768 (–2 15) through +32,767 (+215–1). Arithmetic operations that generate results outside the range of an INTEGER set the overflow flags in the processor status word (PSW). The numeric result is the same as the result of the equivalent operation on WORD variables.

INTEGERs must be aligned at even byte boundaries in the address space. The least-significant byte of the INTEGER is in the even byte address, and the most-significant byte is in the next high- er (odd) address. The address of an INTEGER is that of its least-significant byte (the even byte address). INTEGER operations to odd addresses are not guaranteed to operate in a consistent manner.

3.1.6DOUBLE-WORD Operands

ADOUBLE-WORD is an unsigned, 32-bit variable that can take on values from 0 through 4,294,967,295 (232–1). The architecture directly supports DOUBLE-WORD operands only as the operand in shift operations, as the dividend in 32-by-16 divide operations, and as the product of 16-by-16 multiply operations. For these operations, a DOUBLE-WORD variable must reside in the lower register file and must be aligned at an address that is evenly divisible by four. The address of a DOUBLE-WORD is that of its least-significant byte (the even byte address). The least-significant word of the DOUBLE-WORD is always in the lower address, even when the data is in the stack. This means that the most-significant word must be pushed into the stack first.

DOUBLE-WORD operations that are not directly supported can be easily implemented with two WORD operations. For example, the following sequences of 16-bit operations perform a 32-bit addition and a 32-bit subtraction, respectively.

ADD	REG1,REG3	;	(2-operand	addition)
ADDC	REG2,REG4
SUB	REG1,REG3	;	(2-operand	subtraction)

SUBC REG2,REG4

3-3