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CHAPTER 1 GUIDE TO THIS MANUAL
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1-6
Table 1-1. Handbooks and Product Information
Table 1-2. Application Notes, Application Briefs, and Article Reprints
1-7
GUIDE TO THIS MANUAL
Table 1-3. MCS 96 Microcontroller Datasheets (Commercial/Express)
Table 1-4. MCS 96 Microcontroller Datasheets (Automotive)
Table 1-2. Application Notes, Application Briefs, and Article Reprints (Continued)
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CHAPTER 2 ARCHITECTURAL OVERVIEW
2-2
Table 2-1. Features of the 8XC196M
Product Family
2-3
ARCHITECTURAL OVERVIEW
Figure 2-2. Block Diagram of the Core
Figure 2-1. 8XC196M
Block Diagram
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3-1
CHAPTER 3 PROGRAMMING CONSIDERATIONS
NOTE
Table 3-1. Operand Type Definitions
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CHAPTER 4 MEMORY PARTITIONS
4-2
NOTE
Table 4-1. Memory Map
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4-6
Table 4-4. Peripheral SFRs 8XC196MC
4-7
Table 4-5. Peripheral SFRs 8XC196MD
4-8
Table 4-6. Peripheral SFRs 8XC196MH
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4-13
Figure 4-3. Window Selection (WSR) Register Table 4-9. Selecting a Window of Peripheral SFRs
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4-15
Table 4-11. Windows
Table 4-12. Windowed Base Addresses
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4-17
4.2.2.5 Using the Linker Locator to Set Up a Window
4-18
This listing shows the disasse mbled code:
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CHAPTER 5 STANDARD AND PTS INTERRUPTS
5-2
Figure 5-1. Flow Diagram for PTS and Standard Interrupts
5-3
Table 5-1. Interrupt Signals
Table 5-2. Interrupt and PTS Control and Status Registers
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5-5
Table 5-3. Interrupt Sources, Vectors, and Priorities
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5-8
x
Figure 5-3. Flow Diagram for the OVRTM Interrupt
x
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5-11
Figure 5-4. Standard Interrupt Response Time 5.4.2.2 PTS Interrupt Latency
Figure 5-5. PTS Interrupt Response Time
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5-14
Figure 5-6. PTS Select (PTSSEL) Register
5-15
Figure 5-7. Interrupt Mask (INT_MASK) Register
5-16
Figure 5-8. Interrupt Mask 1 (INT_MASK1) Register
5-17
Figure 5-9. Peripheral Interrupt Mask (PI_MASK) Register
5-18
Figure 5-9. Peripheral Interrupt Mask (PI_MASK) Register (Continued)
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5-21
Figure 5-10. Interrupt Pending (INT_PEND) Register
5-22
Figure 5-11. Interrupt Pending 1 (INT_PEND1) Register
5-23
Figure 5-12. Peripheral Interrupt Pending (PI_PEND) Register
5-24
Figure 5-12. Peripheral Interrupt Pending (PI_PEND) Register (Continued)
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5-26
Figure 5-14. PTS Service (PTSSRV) Register
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5-28
Figure 5-16. PTS Control Block Single Transfer Mode
5-29
Figure 5-16. PTS Control Block Single Transfer Mode (Continued)
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5-31
Figure 5-17. PTS Control Block Block Transfer Mode
5-32
Figure 5-17. PTS Control Block Block Transfer Mode (Continued)
5-33
Figure 5-18. PTS Control Block A/D Scan Mode
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5-38
Figure 5-19. PTS Control Block 1 Serial I/O Mode
5-39
Figure 5-19. PTS Control Block 1 Serial I/O Mode (Conti nued)
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5-41
Figure 5-20. PTS Control Block 2 Serial I/O Mode
5-42
Figure 5-20. PTS Control Block 2 Serial I/O Mode (Conti nued)
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5-54
Figure 5-26. Asynchronous SIO Transmit Mode End-of-PTS Interrupt Routine Flowchart
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5-58
Figure 5-28. Asynchronous SIO Receive Mode End-of-PTS Interrupt Routine Flowchart
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CHAPTER 6 I/O PORTS
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6-3
Figure 6-1. Standard Input-only Port Structure
Table 6-3. Input-only Port Registers
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6-5
Table 6-4. Bidirectional Port Pins
6-6
Table 6-5. Bidirectional Port Control and Status Registers
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6-8
A0238-04
Figure 6-2. Bidirectional Port Structure
6-9
Table 6-6. Logic Table for Bidirectional Ports in I/O Mode
Table 6-7. Logic Table for Bidirectional Ports in Special-function Mode
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6-11
Table 6-8. Control Register Values for Each Configuration
Table 6-9. Port Configuration Example
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6-18
Figure 6-4. Output-only Port
Figure 6-5. Port 6 Output Configuration (WG_OUTPUT) Register
6-19
Figure 6-5. Port 6 Output Configuration (WG_OUTPUT) Register (Continued)
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CHAPTER 7 SERIAL I/O (SIO) PORT
7-2
Table 7-1. Serial Port Signals
Table 7-2. Serial Port Control and Status Registers
7-3
Table 7-2. Serial Port Control and Status Registers (Continued)
7-4
Table 7-2. Serial Port Control and Status Registers (Continued)
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7-11
_CON) Register (Continued)
Figure 7-6. Serial Port Control (SP
7-12
_BAUD) Register
Baud Rate (SP
Figure 7-7. Serial Port
WARNING
7-13
_BAUD) Register (Continued)
Baud Rate (SP
Figure 7-7. Serial Port
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7-15
_STATUS) Register
(SP
Figure 7-8. Serial Port Status
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CHAPTER 8 FREQUENCY GENERATOR
8-2
Table 8-1. Frequency Generator Signal
Table 8-2. Frequency Generator Control and Status Registers
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8-5
Figure 8-4. Infrared Remote Control Application Block Diagram
40 kHz
Zero = 2 ms One = 4 ms
Figure 8-5. Data Encoding Exam ple
8-6
8-7
8-8
8-9
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CHAPTER 9 WAVEFORM GENERA TOR
9-2
x
Figure 9-1. Waveform Generator Block Diagram
9-3
Table 9-1. Waveform Generator Signals
Table 9-2. Waveform Generator Control and Status Registers
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9-8
Table 9-3. Operation in Center-aligned and Edge-aligned Modes
Table 9-4. Register Updates
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9-11
Figure 9-6. Edge-aligned Modes Counter Operation
x
Figure 9-7. Edge-aligned Modes Output Operation
x
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9-13
Figure 9-8. WG Output Configuration (WG_OUTPUT) Register
9-14
Figure 9-8. WG Output Configuration ( WG_OUTPUT) Register (Continued)
9-15
Figure 9-9. Waveform Generator Protection (WG_PROTECT) Register
9-16
Figure 9-10. Waveform Generator Reload (WG_RELOAD) Register
multiplie r
9-17
) Register
Figure 9-11. Phase Compare (WG_COMP
9-18
Figure 9-12. Waveform Generator Control (WG_CONTROL) Register
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9-22
9-23
9-24
9-25
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CHAPTER 10 PULSE-WIDTH MODULAT OR
10-2
Figure 10-1. PWM Block Diagram
Table 10-1. PWM Signals
Port Pin PWM Signal PWM
R S
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10-5
PULSE-WIDTH MODULATOR
where:
Table 10-3. PWM Output Frequencies (FPWM)
10-6
where:
Figure 10-3. PWM Period (PWM_PERIOD) Regi ster
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10-9
PULSE-WIDTH MODULATOR
Figure 10-6. Waveform Generator Output Configuration (WG_OUTPUT) Register
10-10
Figure 10-8. PWM to Analog Conversion Circuitry
Figure 10-7. D/A Buffer Block Diagram
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CHAPTER 11 EVENT PROCESSOR ARRAY (EPA)
11-2
Figure 11-1. EPA Block Diagram
Table 11-2. EPA and Timer/Counter Signals
= 3.
11-3
Table 11-3. EPA Control and Status Registers
Table 11-2. EPA and Timer/Counter Signals (Continued)
11-4
Table 11-3. EPA Control and Status Registers (Continued)
11-5
Table 11-3. EPA Control and Status Registers (Continued)
11-6
Figure 11-2. EPA Timer/Counters
-----------------------------------------------------------
resolution =
4prescaler_divisor F
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11-8
Figure 11-3. Quadrature Mode Interface Table 11-4. Quadrature Mode Truth Table
Optical Reader
X Y
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11-16
Figure 11-8. Timer 1 Control (T1CONTROL) Register
11-17
Figure 11-9. Timer 2 Control (T2CONTROL) Register
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11-19
_CON) Registers
11-20
11-21
11-22
_CON) Registers
Figure 11-11. EPA Compare Control (COMP
11-23
Figure 11-11. EPA Compare Control (COMP
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CHAPTER 12 ANALOG-TO-DIGITAL (A/D) CONVER TER
12-2
Table 12-1. A/D Converter Pins
Table 12-2. A/D Control and Status Registers
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12-7
ANALOG-TO-DIGITAL (A/D) CONVERTER
Figure 12-4. A/D Time (AD_TIME) Register
12-8
Figure 12-5. A/D Command (AD_COMMAND) Register
12-9
ANALOG-TO-DIGITAL (A/D) CONVERTER
Figure 12-6. A/D Result (AD_RESULT) Register Read Format
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12-18
A0085-01
Figure 12-11. Terminal-based A/D Conversion Characteristic
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13-1
CHAPTER 13 MINIMUM HARDWARE CONSIDERATIONS
Table 13-1. Minimum Required Signals
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13-3
MINIMUM HARDWARE CONSIDERATIONS
Figure 13-1. Minimum Hardware Connections
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13-8
Figure 13-7. Reset Timing Sequence
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13-11
MINIMUM HARDWARE CONSIDERATIONS
Figure 13-11. Example of a System Reset Circuit
Figure 13-10. Minimum Reset Circuit
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CHAPTER 14 SPECIAL OPERATING MODES
14-2
Table 14-2. Operating Mode Control and Status Registers
Table 14-1. Operating Mode Control Signals (Continued)
14-3
SPECIAL OPERATING MODES
Table 14-2. Operating Mode Control and Status Registers (Continued)
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14-9
SPECIAL OPERATING MODES
Figure 14-4. Typical Voltage on the VPP Pin While Exiting Powerdown
, Volts
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CHAPTER 15 INTERFACING WITH EXTERNAL MEMORY
15-2
15-3
15-4
Table 15-2. External Memory Interface Registers
15-5
Table 15-3. Register Settings for Configuring External Memory Interfac e Signals
Table 15-2. External Memory Interface Registers (Continued)
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15-7
Figure 15-1. Chip Configuration 0 (CCR0) Register
15-8
Figure 15-1. Chip Configuration 0 (CCR0) Register (Continued)
15-9
Figure 15-2. Chip Configuration 1 (CCR1) Register
15-10
Figure 15-2. Chip Configuration 1 (CCR1) Register
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15-12
Figure 15-4. BUSWIDTH Timing Diagram (8XC196MC, MD)
Figure 15-5. BUSWIDTH Timing Diagram (8XC196MH)
The CLKOUT pin is available only on the 8XC196MC, MD.
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15-15
Figure 15-6. Timings for 16-bit Buses
The CLKOUT pin is available only on the 8XC196MC, MD.
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15-19
Figure 15-8. READY Timing Diagram One Wait State (8XC196MC, M D)
The CLKOUT pin is available only on the 8XC196MC, MD.
15-20
15-21
Table 15-6. Bus-control Modes
Table 15-5. READY Signal Timing Definitions (Continued)
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15-23
Figure 15-12. 8-bit System with Flash and RAM
15-24
Figure 15-13. 16-bit System with Dynamic Bus Width
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15-26
Figure 15-15. 16-bit System with Writes to Byte-wide RAMs
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15-29
Figure 15-19. 16-bit System with EPROM
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15-31
Figure 15-21. 16-bit System with RAM
15-32
Figure 15-22. System Bus Timing
The CLKOUT pin is available only on the 8XC196MC, MD.
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15-34
Table 15-9. Microcontroller Meets These Specifications
15-35
Table 15-9. Microcontroller Meets These Specifications (Continued)
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CHAPTER 16 PROGRAMMING THE NONVOLAT ILE ME MO RY
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16-7
Figure 16-1. Unerasable PROM (USFR) Register
Table 16-4. UPROM Programming Values and Locations for Slave Mode
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16-11
Figure 16-4. Pin Functions in Programming Modes
Table 16-6. Pin Descriptions
16-12
Table 16-6. Pin Descriptions (Continued)
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16-16
Figure 16-5. Slave Programming Circuit
Table 16-8. Device Signature Word and Programming Voltages
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16-18
Figure 16-6. Chip Configuration Registers (CCRs)
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16-20
Figure 16-7. Address/Command Decoding Routine
16-21
Figure 16-8. Program Word Routine
16-22
Measure from falling edge of last PROG# pulse in sequence.
Figure 16-9. Program Word Waveform
Additional program pulses and verifications.
16-23
Figure 16-10. Dump Word Routine
16-24
Figure 16-11. Dump Word Waveform
Table 16-10. Timing Mnemonics
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16-26
O7:0
ON = Error
x
87C196M
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16-28
Figure 16-13. Auto Programming Routine
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16-31
Figure 16-14. PCCB and UPROM Programming Circuit
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16-33
Figure 16-15. Run-time Programming Code Example
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APPENDIX A INSTRUCTION SET REFERENCE
A-2
Table A-1. Opcode Map (Left Half)
A-3
Table A-1. Opcode Map (Right Half)
A-4
Table A-2. Processor Status Word (PSW) Flags
A-5
Table A-3. Effect of PSW Flags or Specified Conditions on Conditional Jump Instructions
Table A-4. PSW Flag Setting Symbols
A-6
Table A-5 defines the variables that are used in Table A-6 to represent the instruction operands.
lreg
w2_reg
lreg
w2_reg
A-7
Table A-6. Instruction Set
A-8
A-9
A-10
A-11
A-12
A-13
A-14
A-15
A-16
A-17
A-18
A-19
A-20
A-21
A-22
A-23
A-24
A-25
A-26
A-27
A-28
A-29
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A-31
A-32
A-33
A-34
A-35
A-36
A-37
A-38
A-39
A-40
A-41
Table A-7. Instruction Opcodes
A-42
Table A-7. Instruction Opcodes (Continued)
A-43
Table A-7. Instruction Opcodes (Continued)
A-44
Table A-7. Instruction Opcodes (Continued)
A-45
Table A-7. Instruction Opcodes (Continued)
A-46
Table A-7. Instruction Opcodes (Continued)
A-47
Table A-8. Instruction Lengths and Hexadecimal Opcodes
A-48
A-49
A-50
A-51
A-52
Table A-9. Instruction Execution Times (in State Times)
A-53
A-54
A-55
A-56
A-57
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APPENDIX B SIGNAL DESCRIPTIONS
B-2
Table B-2. 8XC196MC Signals Arranged by Functional Categories
B-3
Figure B-1. 8XC196MC 64-lead Shrink DIP (SDIP) Package
U8XC196MC View of component as mounted on PC board
B-4
A3101-02
Figure B-2. 8XC196MC 84-lead PLCC Package
x8XC196MC View of component as mounted on PC board
B-5
Figure B-3. 8XC196MC 80-lead Shrink EIAJ/QFP Package
x8XC196MC View of component as mounted on PC board
B-6
Table B-3. 8XC196MD Signals Arranged by Functional Categories
B-7
A3102-02
Figure B-4. 8XC196MD 84-lead PLCC Package
x8XC196MD View of component as mounted on PC board
B-8
Figure B-5. 8XC196MD 80-lead Shrink EIAJ/QFP Package
x8XC196MD View of component as mounted on PC board
B-9
Table B-4. 8XC196MH Signals Arranged by Functional Categories
B-10
Figure B-6. 8XC196MH 64-lead Shrink DIP (SDIP) Package
x8XC196MH View of component as mounted on PC board
B-11
A2573-03
Figure B-7. 8XC196MH 84-lead PLCC Package
x8XC196MH View of component as mounted on PC board
B-12
Figure B-8. 8XC196MH 80-lead Shrink EIAJ/QFP Package
x8XC196MH View of component as mounted on PC board
B-13
Table B-5. Description of Columns of Table B-6
Name
sampled inputs
Name
B-14
B-15
B-16
B-17
B-18
B-19
B-20
B-21
B-22
B-23
Table B-7. Definition of Status Symbols
Table B-8. 8XC196MC and MD Default Signal Conditions
B-24
Table B-8. 8XC196MC and MD Default Signal Conditions (Continued)
B-25
Table B-9. 8XC196MH Default Signal Conditions
B-26
Table B-9. 8XC196MH Default Signal Conditions (Continued)
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C-1
APPENDIX C REGISTERS
Table C-1. Modules and Related Registers
C-2
Table C-2. Register Name, Address, and Reset Status
C-3
C-4
C-5
C-6
AD_COMMAND
C-7
AD_RESULT (Read)
C-8
AD_RESULT (Write)
C-9
AD_TEST
C-10
AD_TIME
C-11
CCR0
C-12
CCR0
C-13
CCR1
C-14
CCR1
C-15
COMPx_CON
C-16
COMPx_CON
C-17
COMPx_TIME
Table C-3. COMP
_TIME Addresses and Reset Values
C-18
C-19
C-20
Table C-4. EPA
_CON Addresses and Reset Values
C-21
EPAx_TIME
Tabl e C- 5. EPA
_TIME Addresses and Reset Values
C-22
FREQ_CNT
C-23
FREQ_GEN
C-24
GEN_CON
C-25
INT_MASK
C-26
INT_MASK1
C-27
INT_PEND
C-28
INT_PEND1
ONES_REG
C-30
Px_DIR
Table C-6. P
_DIR Addresses and Reset Values
C-31
Px_MODE
Table C-7. P
_MODE Addresses and Reset Values
C-32
Px_MODE
Table C-8. Special-function Signals for Ports 1, 2, 5, 6
C-33
Px_PIN
Table C-9. P
_PIN Addresses and Reset Values
C-34
Px_REG
Table C-10. P
_REG Addresses and Reset Values
C-35
PI_MASK
C-36
PI_MASK
C-37
PI_PEND
C-38
PI_PEND
C-39
PPW
C-40
PSW
test_reg
C-41
PSW
test_reg
maskable interrupts
C-42
PTSSEL
C-43
PTSSRV
C-44
PWM_COUNT
C-45
PWM_PERIOD
C-46
PWMx_CONTROL
C-47
SBUFx_RX
C-48
SBUFx_TX
C-49
SP
C-50
SPx_BAUD
C-51
SPx_CON
C-52
SPx_STATUS
C-53
T1CONTROL
C-54
T1RELOAD
C-55
T2CONTROL
C-56
TIMERx
C-57
USFR
C-58
WATCHDOG
C-59
WG_COMPx
C-60
WG_CONTROL
C-61
WG_COUNTER
C-62
WG_OUTPUT (Port 6)
C-63
C-64
C-65
Table C-11. Output Configuration
C-66
WG_PROTECT
C-67
WG_RELOAD
multiplie r
C-68
Table C-12. WSR Settings and Direct Addresses for Windowable SFRs
C-69
Table C-12. WSR Settings and Direct Addresses for Windowable SFRs (Continued)
C-70
Table C-12. WSR Settings and Direct Addresses for Windowable SFRs (Continued)
ZERO_REG
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GLOSSARY
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INDEX
A
B
C
D
E
F
H
I
J
L
M
N
O
P
Page
Q
R
Page
S
T
U
V
W
X
Y
Z
