Intel 8XC196MD, 8XC196MH, 8XC196MC manual Pimask

8XC196MC, MD, MH USER’S MANUAL

PI_MASK

PI_MASK (Continued)	Address:	1FBCH
	Reset State:	AAH

The peripheral interrupt mask (PI_MASK) register enables or disables (masks) interrupt requests associated with the peripheral interrupt (PI), the serial port interrupt (SPI), and the overflow/underflow timer interrupt (OVRTM).

	7
8XC196MC	—	—	—	WG
	7
8XC196MD	—	COMP5	—	WG
	7
8XC196MH	—	SP1	—	SP0

			0
—	OVRTM2	—	OVRTM1
			0
—	OVRTM2	—	OVRTM1
			0
—	OVRTM2	—	OVRTM1

Bit	Bit	Function
Number	Mnemonic
0	OVRTM1	Timer 1 Overflow/Underflow
		Setting this bit enables the timer 1 overflow/underflow interrupt.
		The timer 1 and timer 2 overflow/underflow interrupts are associated with
		the overflow/underflow timer interrupt (OVRTM). Setting INT_MASK.0
		enables OVRTM.

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