Intel 8XC196MD, 8XC196MH Standard Input-only Port Operation, Input-only Port Registers, 1FDAH MH

I/O PORTS

Table 6-3. Input-only Port Registers

Mnemonic	Address	Description
P0_PIN	1FA8H (MC, MD)	Each bit of P0_PIN reflects the current state of the corresponding
	1FDAH (MH)	port 0 pin.
P1_PIN (MC, MD)	1FA9H (MC, MD)	Each bit of P1_PIN reflects the current state of the corresponding
		port 1 pin.

6.2.1Standard Input-only Port Operation

Figure 6-1 is a schematic of an input-only port pin. Transistors Q1 and Q2 serve as electrostatic discharge (ESD) protection devices; they are referenced to VREF and ANGND. Transistor Q3 is an additional ESD protection device; it is referenced to VSS (digital ground). Resistor R1 limits current flow through Q3 to acceptable levels. At this point, the input signal is sent to the analog multiplexer and to the digital level-translation buffer. The level-translation buffer converts the in- put signals to work with the VCC and VSS digital voltage levels used by the CPU core. This buffer is Schmitt-triggered for improved noise immunity. The signals are latched in the P0_PIN or P1_PIN register and are output onto the internal bus when P0_PIN or P1_PIN is read.

Internal Bus		Vcc			VREF	VREF
			To Analog MUX
	PORT 0		Level			Q1
	Data Register		Translation
Buffer	P0_PIN		Buffer		150 to 200 Ohms	Input Pin
	Q	D
		LE			R1
Read Port	PH1 Clock				Q3	Q2
		Vss	Vss	Vss	ANGND ANGND
						A0236-01

Figure 6-1. Standard Input-only Port Structure

6-3