Intel 8XC196MH, 8XC196MD manual Enabling the EPA Interrupts, For EPA capture/compare channels 0, 2

EVENT PROCESSOR ARRAY (EPA)

COMPx_CON (Continued)	Address:	See Table 11-3 on
x = 0–3 (8XC196MC, MH)		page 11-3
x = 0–5 (8XC196MD)	Reset State:	00H

The EPA compare control (COMPx_CON) registers determine the function of the EPA compare channels.

x = 0, 2, 4

x = 1, 3, 5

7

TB	CE	M1	M0
7
TB	CE	M1	M0

0

RE	WGR	ROT	RT
			0
RE	AD	ROT	RT

2

1

0

WGR	A/D Conversion, Waveform Generator Reload
AD	The function of this bit depends on the EPA channel.
	For EPA capture/compare channels 0, 2, 4:
	The WGR bit allows you to use the EPA activities to cause the reload of
	new values in the waveform generator.
	0 = no action
	1 = enables waveform generator reload
	For EPA capture/compare channels 1, 3, 5:
	The AD bit allows you to use the EPA activities to start an A/D
	conversion that has been previously set up in the A/D control registers.
	0 = causes no A/D action
	1 = starts an A/D conversion on an output compare
ROT	Reset Opposite Timer
	Selects the timer that is to be reset if the RT bit is set.
	0 = selects the reference timer for possible reset
	1 = selects the opposite timer for possible reset
	The state of the TB bit determines which timer is the reference timer and
	which timer is the opposite timer.
RT	Reset Timer
	This bit controls whether the timer selected by the ROT bit will be reset.
	1 = resets the timer selected by the ROT bit
	0 = disables the reset function

Figure 11-11. EPA Compare Control (COMPx_CON) Registers (Continued)

11.6 ENABLING THE EPA INTERRUPTS

To enable the interrupts, set the corresponding bits in the INT_MASK register (Figure 5-7 on page 5-15). To enable the individual sources of the multiplexed PI (MC, MD), SPI (MH), and OVRTM (Mx) interrupts, set the corresponding bits in the PI_MASK register (Figure 5-9 on page 5-17). Chapter 5, “Standard and PTS Interrupts,” discusses the interrupts in greater detail.

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