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Intel 8XC196MC, 8XC196MD, 8XC196MH manual Table C-2. Register Name, Address, and Reset Status

Models: 8XC196MD 8XC196MH 8XC196MC

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8XC196MC, MD, MH USER’S MANUAL

Table C-2. Register Name, Address, and Reset Status

	Register	Register Name		Hex	Binary Reset Value
	Register			Hex
	Mnemonic			Addr	High		Low
	Mnemonic			Addr


	AD_COMMAND	A/D Command		1FAC			1000	0000

	AD_RESULT (MC, MD)	A/D Result		1FAA	1111	1111	1100	0000
	AD_RESULT (MH)	A/D Result		1FAA	0111	1111	1100	0000
	AD_RESULT (MH)				0111	1111	1100	0000

	AD_TEST (MC, MD)	A/D Test		1FAE			1100	0000
	AD_TEST (MH)	A/D Test		1FAE			1000	1000
	AD_TEST (MH)						1000	1000

	AD_TIME	A/D Time		1FAF			1111	1111

	CCR0	Chip Configuration 0		†††			XXXX	XXXX

	CCR1	Chip Configuration 1		†††			XXXX	XXXX

	COMP0_CON	EPA Compare 0 Control		1F58			0000	0000

	COMP1_CON	EPA Compare 1 Control		1F5C			0000	0000

	COMP2_CON	EPA Compare 2 Control		1F60			0000	0000

	COMP3_CON (MC, MD)	EPA Compare 3 Control		1F64			0000	0000
	COMP3_CON (MH)
				1F4C
				1F4C

	COMP4_CON (MD)	EPA Compare 4 Control		1F68			0000	0000

	COMP5_CON (MD)	EPA Compare 5 Control		1F6C			0000	0000

	COMP0_TIME	EPA Compare 0 Time		1F5A	XXXX	XXXX	XXXX	XXXX

	COMP1_TIME	EPA Compare 1 Time		1F5E	XXXX	XXXX	XXXX	XXXX

	COMP2_TIME	EPA Compare 2 Time		1F62	XXXX	XXXX	XXXX	XXXX

	COMP3_TIME (MC, MD)	EPA Compare 3 Time		1F66	XXXX	XXXX	XXXX	XXXX
	COMP3_TIME (MH)
				1F4E
				1F4E

	COMP4_TIME (MD)	EPA Compare 4 Time		1F6A	XXXX	XXXX	XXXX	XXXX

	COMP5_TIME (MD)	EPA Compare 5 Time		1F6E	XXXX	XXXX	XXXX	XXXX

	EPA0_CON	EPA Capture/Comp 0 Control		1F40			0000	0000

	EPA1_CON	EPA Capture/Comp 1 Control		1F44			0000	0000

	EPA2_CON (MC, MD)	EPA Capture/Comp 2 Control		1F48			0000	0000

	EPA3_CON (MC, MD)	EPA Capture/Comp 3 Control		1F4C			0000	0000

	EPA4_CON (MD)	EPA Capture/Comp 4 Control		1F50			0000	0000

	EPA5_CON (MD)	EPA Capture/Comp 5 Control		1F54			0000	0000

	EPA0_TIME	EPA Capture/Comp 0 Time		1F42	XXXX	XXXX	XXXX	XXXX

†Reset value is FFH when pin is not driven.

††Reset value is 80H if the EA# pin is high, A9H if EA# is low.

†††The CCRs are loaded with the contents of the chip configuration bytes (CCBs) after a device reset, unless the device is entering programming modes (see “Entering Programming Modes” on page

16-13), in which case the programming chip configuration bytes (PCCBs) are used. The CCBs reside in internal nonvolatile memory at addresses 2018H (CCB0) and 201AH (CCB1).

C-2

Image 479

Intel 8XC196MC, 8XC196MD, 8XC196MH manual Table C-2. Register Name, Address, and Reset Status

Contents

8XC196MC, 8XC196MD, 8XC196MH Microcontroller User’ Manual We Value Your Opinion Page 8XC196MC, 8XC196MD, 8XC196MH Microcontroller User’s Manual Intel Corporation Contents Chapter Memory Partitions Contents 8XC196MC, MD, MH USER’S Manual Programming the Waveform Generator PWM Signals and RegistersFunctional Overview Programming the Frequency Generator Application ExampleChapter Event Processor Array EPA Chapter Minimum Hardware Considerations Chapter Programming the Nonvolatile Memory Appendix C Registers Glossary Index Figures 10-5 15-9 Ready Timing Diagram One Wait State 8XC196MH 15-21 Tables 11-12 16-7 Pmode Values Guide to This Manual Page Chapter Guide to this Manual Manual ContentsSpecial Operating Modes Assert and deassert Notational Conventions and TerminologyNumbers Related Documents Title Order Number Handbooks and Product InformationApplication Notes, Application Briefs, and Article Reprints MCS 96 Microcontroller Datasheets Automotive MCS 96 Microcontroller Datasheets Commercial/ExpressThis Page Left Intentionally Blank Guide to this Manual This Page Left Intentionally Blank Product Literature World Wide WebTechnical Support Page Architectural Overview Page Typical Applications Microcontroller FeaturesSIO PWM Features of the 8XC196Mx Product FamilyFunctional Overview OtpromRAM ROMPTS EPA PWM WDT SIO CPURegister Arithmetic-logic Unit Ralu CPU ControlRegister File Instruction Format Code ExecutionMemory Interface Unit Interrupt ServiceClock Circuitry Internal TimingState Times at Various Frequencies Internal PeripheralsSerial I/O SIO Port 1 I/O PortsWaveform Generator Event Processor Array EPA and Timer/CountersPulse-width Modulator PWM Frequency GeneratorAnalog-to-digital Converter Watchdog TimerReducing Power Consumption Testing the Printed Circuit BoardProgramming the Nonvolatile Memory Programming Considerations Page Restrictions Overview of the Instruction SETOperand Type Definitions Operand Type No. Signed Possible Values AddressingWord Operands BIT OperandsByte Operands SHORT-INTEGER OperandsDOUBLE-WORD Operands Integer OperandsFloating Point Operations LONG-INTEGER OperandsConverting Operands Conditional JumpsAddressing Modes Definition of Temporary Registers Direct AddressingImmediate Addressing Indirect AddressingShort-indexed Addressing Indexed AddressingIndirect Addressing with Autoincrement Indirect Addressing with the Stack PointerZero-indexed Addressing Long-indexed AddressingSoftware Standards and Conventions Assembly Language Addressing Mode SelectionsUsing Registers Linking Subroutines Addressing 32-bit OperandsSoftware Protection Features and Guidelines 8XC196MC, MD, MH USER’S Manual Memory Partitions Page Program and Special-purpose Memory Memory PartitionsExternal Devices Memory or I/O Description Addressing Modes Program MemoryMemory Map DeviceInterrupt and PTS Vectors Special-purpose MemorySpecial-purpose Memory Addresses Reserved Memory LocationsSecurity Key Chip Configuration Bytes CCBsSpecial-function Registers SFRs Peripheral SFRs Memory-mapped SFRsSFRs EPA and Timer SFRsPeripheral SFRs 8XC196MC Port 2 SFRsPorts 2 and 7 SFRs Peripheral SFRs 8XC196MDSerial I/O Port SFRs Peripheral SFRs 8XC196MHPort 0 and 2 SFRs Port 1 SFRsAddress Register File Memory MapDevice and Hex Address Range Description Addressing Modes Register File Memory AddressesGeneral-purpose Register RAM Stack Pointer SPAddress High Odd Byte Low Even Byte CPU Special-function Registers SFRsCPU SFRs 00FFH Windowing8XC196MC,MD 02FFH 01FFHWSR Value for Peripherals Selecting a WindowWSR Bit Function Number10. Selecting a Window of the Upper Register File Addressing a Location Through a WindowPeripheral SFRs 11. Windows12. Windowed Base Addresses Base WSR Value WSR Value forUnsupported Locations Windowing Example 2.1 32-byte Windowing Example2.2 64-byte Windowing Example 2.3 128-byte Windowing Example?WSR Using the Linker Locator to Set Up a WindowThis listing shows the disassembled code LDB WSR, #12H Windowing and Addressing ModesPage Standard and PTS Interrupts Page Overview of Interrupts Chapter Standard and PTS InterruptsFlow Diagram for PTS and Standard Interrupts Interrupt and PTS Control and Status Registers Interrupt Signals and RegistersInterrupt Signals Ptssrv Interrupt Sources and PrioritiesPipend 1FBEH PtsselInterrupt Source Mnemonic Name Vector Priority Interrupt Controller PTS ServiceInterrupt Sources, Vectors, and Priorities Software Trap Special InterruptsExternal Interrupt Pin Unimplemented OpcodeWaveform Generator Protection Circuitry Multiplexed Interrupt SourcesFlow Diagram for the Ovrtm Interrupt Situations that Increase Interrupt Latency End-of-PTS InterruptsInterrupt Latency Standard Interrupt Latency Calculating LatencyStandard Interrupt Response Time PTS Interrupt Latency Execution Times for PTS Cycles PTS Mode Execution Time in State TimesProgramming the Interrupts Standard and PTS Interrupts Bit Function Ptssel8XC196MC 8XC196MDCOMP2 MC, MD IntmaskCOMP2 EPA2 COMP1 EPA1 COMP3 COMP0 EPA0 Ovrtm Bit Mnemonic Interrupt Standard VectorNMI Extint SPI COMP3 EPA3 COMP4 EPA4 RI1 RI0 TI1 TI0 INTMASK1NMI Extint NMI Extint EPA5Bit Function Number Mnemonic Pimask8XC196MC 8XC196MD OVRTM1 Modifying Interrupt PrioritiesPimask Standard and PTS Interrupts Determining the Source of an Interrupt Intpend 10. Interrupt Pending Intpend RegisterINTPEND1 11. Interrupt Pending 1 INTPEND1 RegisterPipend 12. Peripheral Interrupt Pending Pipend RegisterPipend Initializing the PTS Control BlocksSpecifying the PTS Count Ptssrv 14. PTS Service Ptssrv RegisterPtscon Selecting the PTS ModeSingle Transfer Mode Ptsdst Ptscb + PTS Single Transfer Mode Control BlockPtsdst H Ptsdst L Ptssrc H Ptssrc L Ptscon Ptscount Register Location FunctionStandard and PTS Interrupts Block Transfer Mode Ptscb Block Transfer ModeSingle Transfer Mode Ptscb Ptsblock Ptscb + PTS Block Transfer Mode Control Block5 A/D Scan Mode PTS A/D Scan Mode Control Block Address Contents A/D Scan Mode Command/Data Table5.2 A/D Scan Mode Example 5.1 A/D Scan Mode CyclesPtscount = 04H Command/Data Table ExampleA/D Scan Mode Ptscb Example PTSPTR2 H = 1FH PTSPTR2 L = AAHSerial I/O Modes 5.3 A/D Scan Mode Example10. Command/Data Table Example 11. A/D Scan Mode Ptscb ExamplePtsvec PTS Serial I/O Mode Control Block 1 8XC196MC, MDSA1 SA0 MAJ SA0 † BaudEpareg SA18XC196MC, MD, MH USER’S Manual Port Address Pointer high byte PTS Serial I/O Mode Control Block 2 8XC196MC, MDPort Mask Register Rpar DataPTSCON1 Portreg PTS Serial I/O Mode Control Block8XC196MC, MD Register Location Function 8XC196MC, MD, MH USER’S Manual PTSCB1 PTSCB2 13. Ssio Transmit Mode PTSCBsTxddone = 23. Synchronous SIO Receive Timing Synchronous SIO Receive Mode ExampleClrb Rxddone 14. Ssio Receive Mode PTSCBsStandard and PTS Interrupts Rxddone = 25. Asynchronous SIO Transmit Timing 15. Asio Transmit Mode PTSCBs Standard and PTS Interrupts End-Of-PTS Interrupt Save Critical Data Is PTS 27. Asynchronous SIO Receive Timing Asynchronous SIO Receive Mode ExamplePortreg H = 1FH P2PIN 16. Asio Receive Mode PTSCBsSamptime = 01H Standard and PTS Interrupts End-Of-PTS Interrupt Ports Page Port Bits Type Direction Associated Peripherals I/O Ports OverviewDevice I/O Ports INPUT-ONLY Ports 1 MC, MD only Standard Input-only Port PinsP1PIN MC, MD Standard Input-only Port OperationInput-only Port Registers 1FDAH MHBidirectional Ports 1 MH ONLY, 2, 5, and 7 MD only Standard Input-only Port ConsiderationsPort Pin Special-function Associated Signals Bidirectional Port PinsBidirectional Port Control and Status Registers Bidirectional Port OperationPorts Bidirectional Port Structure Sfdir Bidirectional Port Pin ConfigurationsLogic Table for Bidirectional Ports in I/O Mode 8XC196MC, MD, MH USER’S Manual Port Configuration Example Bidirectional Port Pin Configuration ExampleControl Register Values for Each Configuration HZ1 Bidirectional Port ConsiderationsP5.1/INST 12. Ports 3 and 4 Control and Status Registers Ports 3 and 4 PinsPort Pins Special-function Bidirectional Ports 3 and 4 ADDRESS/DATA BUSAddress/Data Bus Ports 3 and 4 Structure Bidirectional Ports 3 and 4 Address/Data Bus Operation13. Logic Table for Ports 3 and 4 as Open-drain I/O Using Ports 3 and 4 as I/ODesign Considerations for Ports 3 Standard OUTPUT-ONLY Port15. Output-only Port Control Register Configuring Output-only Port Pins14. Standard Output-only Port Pins Output-only Port OperationOP1 OP0 Reset State 0000HWgoutput Port Address 1FC0HWgoutput Port Reset State 0000HPage Serial I/O SIO Port Page Serial I/O SIO Port Functional Overview SIO Block DiagramSerial Port Control and Status Registers Serial I/O Port Signals and RegistersSerial Port Signals P1REG 1F9DH P1DIR 1F9BHP1PIN 1F9FH Serial Port Modes Mode Synchronous Modes Modes 0Mode 0 Timing Asynchronous Modes Modes 1, 2, Serial Port Frames for Mode Multiprocessor Communications Mode 2 and 3 TimingsSP xCON Address 1F83H, 1F8BH = 0-1 8XC196MH Configuring the Serial Port PinsProgramming the Serial Port Programming the Control RegisterBit Function BV9 BV8 Programming the Baud Rate and Clock SourceClksrc BV7Bclk Baudvalue =E82BH SPxBAUD Values When Using XTAL1 at 16 MHzEnabling the Serial Port Interrupts 80CFHRPE/RB8 Determining Serial Port StatusRPE/RB8 TXE 8XC196MC, MD, MH USER’S Manual Frequency Generator Page Chapter Frequency Generator Port Frequency Frequency Generator SignalFrequency Generator Control and Status Registers Freqgen Configuring the OutputProgramming the Frequency Generator Programming the FrequencyFreqcnt Determining the Current Value of the Down-counterApplication Example Frequency Generator 0FAH Xmitbuf Dsb Bufsize Block of data to send Shiftreg Stb temp,freqgen0 Into freq gen Frequency Generator Page Waveform Generator Page Waveform Generator Functional Overview Chapter Waveform GeneratorWaveform Generator Block Diagram Waveform Generator Control and Status Registers Waveform Generator Signals and RegistersWaveform Generator Signals Timebase Generator Waveform Generator OperationControl and Protection Circuitry Phase Driver ChannelsProtection Circuitry Register Buffering and SynchronizationOperating Modes Step Center-aligned Modes Edge-aligned Modes Register UpdatesEvent Mode Operation in Center-aligned and Edge-aligned ModesCenter-aligned Modes Counter Operation Center-aligned ModesCenter-aligned Modes Output Operation Edge-Aligned Modes Edge-aligned Modes Counter Operation Programming the Waveform Generator Configuring the OutputsOutput Configuration OP1 Wgoutput Waveform GeneratorOP1 OP0 Sync PE7 PE68XC196MC, MD, MH USER’S Manual 8XC196MC, MD 8XC196MH Bit Function Number Mnemonic WgprotectF0H E0H150 Reload Specifying the Carrier Period and Duty CycleWgreload Reload1FC2H,1FC4H,1FC6H Wgcomp AddressWgcounter = Wgreload WgcontrolDT7 DT6 DT5 DT4 DT9 DT8 DT3 DT2 DT1 DT0 Xxxxh Determining the Waveform GENERATOR’S StatusEnabling the Waveform Generator Interrupts WgcounterWgcomp Design ConsiderationsDead Time and Duty Cycle Wgcount WGCOUNT=Programming Example Ph3 Dsw P6.4,5 config Waveform Generator Temp1,WGOUTPUT0 Now store it Ret Demo board PI interrupt Page Pulse-width Modulator Page PWM Functional Overview Chapter PULSE-WIDTH ModulatorPWM Signals PWM Signals and RegistersPEx Pin Output PWM OperationPWM Control and Status Registers FFH Programming the Frequency and PeriodE6H Pwmperiod PWM Output Frequencies FpwmPwmperiod + Programming the Duty CyclePWM xCONTROL Address 10-3 Sample CalculationsReading the Current Value of the Down-counter Pwmcount PWM Output Alternate Port Function PWM Output Enabled WhenEnabling the PWM Outputs PWM Output Alternate FunctionsWaveform Generator Output Configuration Wgoutput Register Generating Analog Outputs D/A Buffer Block DiagramEvent Processor Array EPA Page COMP30 EPA Functional OverviewEPA Channels Device Capture/Compare Channels Compare-only ChannelsEPA and Timer/Counter Signals EPA and TIMER/COUNTER Signals and RegistersEPA Control and Status Registers P1PIN 1FA9H P0PIN 1FA8HT1RELOAD TIMER/COUNTER Functional OverviewTIMER1 1F7AH TIMER2 1F7EHEPA Timer/Counters Quadrature Clocking Modes Cascade Mode Timer 2 OnlyT1DIR State of Xinternal State of Yinternal Count DirectionEPA Channel Functional Overview Quadrature Mode Timing and CountA Single EPA Capture/Compare Channel Operating in Capture ModeEPA Simplified Input-capture Structure EPAxCON.0 Action Taken When a Valid Edge OccursOverwrite Bit Status Action Taken When a Valid Edge Occurs EPA OverrunsGenerating a Low-speed PWM Output Operating in Compare ModePreventing EPA Overruns Generating the Highest-speed PWM Output Programming the Timers Programming the EPA and TIMER/COUNTERSConfiguring the EPA and Timer/Counter Signals Clock Source Direction Source Prescaler Divisor Resolution †T1CONTROL T2CONTROL Prescaler Resolution †Programming the Capture/Compare Channels Example EPA Control Register Settings for Channels 1, 3, orMode WGR ROT ON/RT = 0, 2 = 1, 3 Capture Mode EventCompare Mode Action EPAxCON = 0-1 8XC196MH x = 0-3 8XC196MC x = 0-5 8XC196MDFor EPA capture/compare channels 1, 3 EPA xCON Address= 0, 2 For EPA capture/compare channels 0, 2Compare Mode RT Capture Mode onWGR ROT = 0-3 8XC196MC, MH = 0-5 8XC196MD Reset State 00HProgramming the Compare-only Channels Comp xCON AddressEnabling the EPA Interrupts Determining Event Status Analog-to-digital Converter PageNum-38 Angnd 12.1 A/D Converter Functional OverviewA/D Control and Status Registers 12.2 A/D Converter Signals and RegistersA/D Converter Pins Port Pin Signal DescriptionP1PIN MC,MD 12.3 A/D Converter OperationProgramming the A/D Converter OFF1 OFF0 Programming the A/D Test RegisterAdtest Adresult Write Programming the A/D Time RegisterAdtime Programming the A/D Command RegisterACH3 ACH2 ACH1 ACH0 AdcommandM1 M0 Mode Enabling the A/D InterruptADRLT90 Determining A/D Status and Conversion ResultsAdresult Read Idealized A/D Sampling Circuitry Designing External Interface CircuitryMinimizing the Effect of High Input Source Resistance Suggested A/D Input Circuit Using Mixed Analog and Digital Inputs Understanding A/D Conversion Errors12-14 Ideal A/D Conversion Characteristic 10. Actual and Ideal A/D Conversion Characteristics 12-17 11. Terminal-based A/D Conversion Characteristic Minimum Hardware Considerations Page Minimum Connections Minimum Required SignalsRESET# 13.1.2 I/O Port Pin Connections I/O Port Configuration GuidePort Where to Find Configuration Information Unused InputsMinimum Hardware Connections Noise Protection Tips Applying and Removing PowerOn-chip Oscillator Circuit ON-CHIP Oscillator CircuitryExternal Crystal Connections External Clock Connections Using AN External Clock SourceReset Timing Sequence Resetting the DeviceDRO GenconRsts DR0 RstsInternal Reset Circuitry Generating an External Reset10. Minimum Reset Circuit Generating Wait States Issuing the Reset RST InstructionEnabling the Watchdog Timer Issuing an Illegal Idlpd Key Operand1EH A1H Selecting the Watchdog Reset Interval 8XC196MH onlyFirst Byte Second Byte Reset Interval 1EH E1HPage Special Operating Modes Page Clkout Special Operating Mode Signals and RegistersOperating Mode Control Signals Port Pin Signal Type DescriptionCCR0 Operating Mode Control and Status RegistersPort Pin Signal Type Description Name ONCE#P1REG MH 1F9DH Reducing Power ConsumptionP1MODEMH P7MODEMD 1FD1HClock Control During Power-saving Modes Idle ModeEnabling and Disabling Powerdown Mode Powerdown ModeDriving the VPP Pin Low Entering Powerdown ModeExiting Powerdown Mode Generating a Hardware ResetAsserting the External Interrupt Signal Selecting R1 and C1 External RC CircuitTypical Voltage on the VPP Pin While Exiting Powerdown Once Mode Reserved Test Modes Page Interfacing with External Memory Page ADV# External Memory Interface Signals and RegistersExternal Memory Interface Signals Signal Port Pin Type Description NameCCR1.2 Buswidth Bytes AccessedBHE# AD0 CCR0.1WR# Signal Port PinEA# Register Address Description Mnemonic External Memory Interface RegistersWRH# WRL#BHE#/WRH# † Chip Configuration Registers and Chip Configuration BytesP5REG = 11XX Xxxxb 15-6 IRC2 IRC1 IRC0 CCR0LOC1 LOC0 IRC1 IRC0 ALE BW0 LOC1 LOC0BW1 BW0 CCR0ALE WDE CCR1WDE BW1 IRC2 CCR1 BUS Width and MultiplexingMultiplexing and Bus Width Options Buswidth Timing Diagram 8XC196MC, MD Timing Requirements for Buswidth Buswidth Signal Timing DefinitionsSymbol Definition 15.3.2 16-bit Bus Timings Timings for 16-bit Buses 15.3.3 8-bit Bus Timings Timings for 8-bit Buses Wait States Ready Control15-18 Ready Timing Diagram One Wait State 8XC196MC, MD Address Valid to Ready Setup Bus-control Modes Bus-control Mode Bus-control Signals CCR0.3 CCR0.2BUS-CONTROL Modes BHE# WR# AD0 Standard Bus-control ModeALE OE# WE# RD# WR# CS#OE# WE# RD# WR# Buswidth CS#Eprom RAM 14. Write Strobe Mode Write Strobe ModeOE# OE# WE# RD# WRH# WRL# 15 -bit System with Writes to Byte-wide RAMs16. Address Valid Strobe Mode Address Valid Strobe Mode18 -bit System with Flash OE# RD# Eprom20. Timings of Address Valid with Write Strobe Mode Address Valid with Write Strobe ModeWE# CS# System BUS AC Timing SpecificationsVCC Buswidth WRH# WRL# CS#22. System Bus Timing AC Timing Definitions Explanation of AC SymbolsAC Timing Symbol Definitions Signals External Memory Systems Must Meet These SpecificationsAddress Setup to ALE/ADV# Low Microcontroller Meets These Specifications15-35 Page Programming Nonvolatile Memory Page Programming Methods Programming the Nonvolatile MemoryOtprom Memory MAP Address Range Description Hex Security FeaturesControlling Access to Internal Memory C196Mx Otprom Memory MapRead Protect Write Protect Protection Status Controlling Access to the Otprom During Normal OperationMemory Protection for Normal Operating Mode Controlling Access to the Otprom During Programming ModesPccb CCB Memory Protection Options for Programming ModesSecurity Key Controlling Fetches from External Memory To set this bit Write this value To this location Uprom Programming Values and Locations for Slave ModeUsfr BitBitFunction Number Mnemonic Programming Pulse WidthPpwvalue PPWPpwvalue = Modified QUICK-PULSE AlgorithmExample Ppwvalue Calculations 8XC196MC, MD 8XC196MH Two 250-µs pulses requiredModified Quick-pulse Algorithm Special Program Port Pin Programming Mode PinsPACT# PROG#AINC# CpverPmode Values Selecting the Programming ModeEntering Programming Modes Power-down Sequence Power-up and Power-down SequencesPower-up Sequence Reading the Signature Word and Programming Voltages Slave Programming ModeLocation Value Slave Programming Circuit and Memory MapDevice Signature Word and Programming Voltages Device Signature Word Programming VCCDescription Address Comments Slave Programming Mode Memory MapOperating Environment Bit Mnemonic Function CCR1, CCR0LOC1 LOC0 IRC1 IRC0 WDE BW1 IRC2 Slave Programming Routines Address/Command Decoding Routine Program Word Routine Program Word Waveform 10. Dump Word Routine MnemonicDescription Timing Mnemonics10. Timing Mnemonics Mnemonic Description Auto Programming ModeAuto Programming Circuit and Memory Map 12. Auto Programming Circuit 11 XC196MC/MD Auto Programming Memory Map Address Internal Address Using Output fromAddress Internal Address Using Auto Programming Routine13. Auto Programming Routine Auto Programming Procedure Pccb and Uprom Programming 8XC196MH only ROM-dump Mode14. Pccb and Uprom Programming Circuit PMODE30 0DH Pins Pccb Programming Uprom ProgrammingRUN-TIME Programming 13. Pccb and Uprom Programming Values15. Run-time Programming Code Example Page Instruction Set Reference Page Appendix a Instruction SET Reference Opcode Table A-1. Opcode Map Left HalfTable A-1. Opcode Map Right Half Instruction Quotient Stored Flag Set if Quotient is Table A-2. Processor Status Word PSW FlagsValue of Bits Shifted Off Instruction Jumps to Destination if Continues if Table A-4. PSW Flag Setting SymbolsSymbol Description Variable Description Table A-5. Operand VariablesC V VT ST PSW Flag SettingsTable A-6. Instruction Set Mnemonic OperationAndb Instruction FormatDest ← Dest and SRC Count PTRS, CntregDest Count ← Cntreg Loop Srcptr ← Ptrs DstptrDstptr ← Srcptr Ptrs ← Srcptr + Count ← CountClear BYTE. Clears the value Mnemonic Operation Instruction Format Dest MOD SRC ← Dest MOD SRCDjnzw Decrement and Jump if not Zero Djnz Decrement and Jump if not ZeroEXT SIGN-EXTEND Integer Into Long Dpts Disable Peripheral TransactionEpts Enable Peripheral Transaction EptsExtb SIGN-EXTEND SHORT-INTEGER Into Increment BYTE. Increments the value Byte operand by JGE Jump if Signed Greater than or JLE Jump if Signed Less than or Equal Negative flag is set, this instruction adds JNV Jump if Overflow Flag is Clear Jnvt Jump if OVERFLOW-TRAP Flag is JVT Jump if OVERFLOW-TRAP Flag is SET Load Byte SIGN-EXTENDED. Sign Mulb MULMulub MuluSRC, Dest Integer operandDest ← Dest or SRC Dest ← not DestPSW/INTMASK ← SP INTMASK1/WSR ← SPSP ← INTMASK1/WSR INTMASK1 ← SP ← PSW/INTMASK PSW/INTMASK ←Scall Wreg, #count SHR Range of 0 to 31 1FH, inclusive. If Shral Arithmetic Right Shift Double Skip Shrl Logical Right Shift DOUBLE-WORDSUB Rightmost operandSubcb Subtract Bytes with Borrow DEST, SRC SubbSubc Subtract Words with Borrow DEST, SRC SubcTijmp TBASE, INDEX, #MASK Index and #MASK = Offset× Offset + Tbase = Dest Dest ← Dest XOR SRC XORDecb Extb Incb Shrb Shlb Shrab Table A-7. Instruction OpcodesHex Code Instruction Mnemonic Clrb Notb NegbHex Code Hex Code 8XC196MC, MD, MH USER’S Manual EF Lcall Dpts EptsDIV/DIVB/MUL/MULB Note Subc Subcb Table A-8. Instruction Lengths and Hexadecimal OpcodesArithmetic Group Direct Immediate Indirect Indexed Mnemonic Logical Direct Immediate Indirect Jump Direct Stack Direct Immediate Indirect Indexed MnemonicOpcode Length Data DirectConditional Jump Direct Immediate Call Direct Immediate Indirect Indexed MnemonicLength Opcode Mnemonic Direct Immediate Indirect Shift Mnemonic Direct Immediate Indirect IndexedSpecial Mnemonic Direct Immediate Indirect PTSMem Reg Table A-9. Instruction Execution Times in State TimesArithmetic Group Indirect Normal Autoinc Short Long Reg MemLogical Mnemonic Direct Immed Normal Autoinc Short Long Reg MemDIV Divb Divu Divub Reg Mem Stack Register IndirectNormal Autoinc Short Ljmp Sjmp Tijmp Autoinc Short Long RegLDB Ldbse Ldbze STB XCH Xchb Autoinc Short LongConditional Jump Mnemonic Call Memory Indirect Indexed Mnemonic DirectNormal Autoinc Short Long NOP RST Setc Skip Shift Mnemonic DirectIndirect Indexed Clrc Clrvt IdlpdPage Signal Descriptions Page New Name Signal Name ChangesFunctional Groupings of Signals Table B-1. Signal Name ChangesTable B-2 XC196MC Signals Arranged by Functional Categories U8XC196MC Figure B-1 XC196MC 64-lead Shrink DIP Sdip PackageX8XC196MC Figure B-2 XC196MC 84-lead Plcc PackageFigure B-3 XC196MC 80-lead Shrink EIAJ/QFP Package P7.7/FREQOUT Table B-3 XC196MD Signals Arranged by Functional CategoriesX8XC196MD Figure B-4 XC196MD 84-lead Plcc PackageFigure B-5 XC196MD 80-lead Shrink EIAJ/QFP Package P2.7/SCLK1#/BCLK1 Table B-4 XC196MH Signals Arranged by Functional CategoriesEA# Extint NMI ONCE# RESET# XTAL1 XTAL2 X8XC196MH Figure B-6 XC196MH 64-lead Shrink DIP Sdip PackageFigure B-7 XC196MH 84-lead Plcc Package Figure B-8 XC196MH 80-lead Shrink EIAJ/QFP Package Signal DescriptionsColumn Heading Description Name Table B-6. Signal DescriptionsTable B-5. Description of Columns of Table B-6 BCLK10 COMP1/P2.5/PACT#, COMP2/P2.6/CPVER, COMP3/P2.7MC, MD CCR0.1 CCR1.2Buswidth Command that invoked the power-saving mode System using a clip-on emulator P5.7/BUSWIDTH PMODE.30 Slave programmingAuto programming Programming Start SCLK10# Shift Clock 0 MH only Default Conditions Functions RESET# Active Table B-7. Definition of Status SymbolsTable B-8 XC196MC and MD Default Signal Conditions Port Signals Alternate During Upon RESET#PWM0 WK0 NMI WK0 RESET#WG2 WK1 WG3 WK1Alternate During Upon Table B-9 XC196MH Default Signal ConditionsRESET# Port SignalsOsc output Registers Page 8XC196MC, MH, x = Table C-1. Modules and Related RegistersCPU Table C-2. Register Name, Address, and Reset Status Xxxx EPA5TIME MD Xxxx EPA2TIME MC, MDXxxx EPA3TIME MC, MD Xxxx EPA4TIME MDP5REG MC, MD P7PIN MDXxxx P1REG MH 1FFDUsfr MH Xxxx Watchdog Xxxx TIMER1TIMER2 Usfr MC, MDAdcommand Adresult Read Adresult Write Adtest Adtime CCR0 ALE CCR1 IRC2 IRC1 IRC0 Comp xCON Address Table C-3 = 0-3 8XC196MC, MH COMPxCONFor EPA capture/compare channels 0, 2 Comp xTIME Address Table C-3. COMPxTIME Addresses and Reset ValuesRegister Address Reset Value COMPxTIMEEPAxCON = 0-3 8XC196MC x = 0-5 8XC196MD EPAxCON Address Table C-4 = 0-1 8XC196MH= 0-3 8XC196MC = 0-5 8XC196MD Table C-4. EPAxCON Addresses and Reset ValuesEPAxTIME = 0-1 8XC196MH x = 0-3 8XC196MC x = 0-5 8XC196MD Table C-5. EPAxTIME Addresses and Reset ValuesEPA Timer Value EPAxTIMEFreqcnt Freqgen Gencon OVRTM† IntmaskINTMASK1 Intpend INTPEND1 One OnesregOnesreg Ffffh= 2, 5 M Table C-6. PxDIR Addresses and Reset ValuesPxDIR = 1 MHPIN7 PIN6 PIN5 PIN4 Table C-7. PxMODE Addresses and Reset ValuesPxMODE = 1 MH = 2, 5 Mx8XC196MC, MD Table C-8. Special-function Signals for Ports 1, 2, 5Pin Special-function Signal PortPxPIN Table C-9. PxPIN Addresses and Reset Values= 2-5 M Table C-10. PxREG Addresses and Reset ValuesPxREG PxREG = 2-5 8XC196MC = 2-5, 7 8XC196MD x = 1-5 8XC196MHPimask Pimask Pipend Pipend PPW150 Ppwvalue PPWPSE PSWPSW PSW Ptssel Ptssrv Pwmcount Pwmperiod PWM xCONTROL Address 1FB0H, 1FB2H PWMxCONTROL8XC196MH Data Received Bit SBUFxRXSBUFxRX Address 1F80H, 1F88H = 0-1 8XC196MH 8XC196MH Data to Transmit Bit SBUFxTXSbuf xTX Address 1F82H, 1F8AH = 0-1 8XC196MH 150 Stack Pointer Stack PointerSPxBAUD SPxCON Address 1F83H, 1F8BH = 0-1 8XC196MH SPxCONSPxSTATUS T1CONTROL T1RELOAD Timer 1 Reload ValueT1RELOAD T2CONTROL 1F7EH TIMERxTimer Address 1F7AH Usfr 0AH WatchdogWatchdog WGCOMPx Wgcontrol Wgcounter Wgoutput Port Wgoutput Waveform Generator Wgoutput Waveform Generator Output Values Output Polarities WG x# Table C-11. Output ConfigurationWgprotect Wgreload 00E0-00FFH 00C0-00FFH WSRByte Windows Register Mnemonic00E0-00FFH 00C0-00FFH 0080-00FFH Location PWM1CONTROL 1FB2H 7DH T2CONTROL 1F7CH 7BH 00FCH 3DH 1EH TIMER1 † 1F7AH 00FAH1EH 00FAH TIMER2 † 1F7EH 7BH 00FEH 3DH WGCOMP1 1FC2H PWM0CONTROL 1FB0H 7DHZero ZeroregZeroreg Page Glossary Page Glossary Characteristic DOUBLE-WORD LONG-INTEGER LSB Otprom PTS PWM SFR Special interrupt WDT Page Index Page Index Index-2 Index-3 Index-4 Index-5 Index-6 Index-7 Index-8 Index-9 Index-10 Index-11 Index-12 Index-13 Index-14