Intel 8XC196MH, 8XC196MD, 8XC196MC manual Standard Input-only Port Considerations

8XC196MC, MD, MH USER’S MANUAL

6.2.2Standard Input-only Port Considerations

Port 0 and 1 pins are unique in that they may individually be used as digital inputs and analog inputs at the same time. However, reading the port induces noise into the A/D converter, decreas- ing the accuracy of any conversion in progress. We strongly recommend that you not read the port while an A/D conversion is in progress. To reduce noise, the P0_PIN or P1_PIN register is clocked only when the port is read.

These port pins are powered by the analog reference voltage (VREF) and analog ground (ANGND) pins. If the port pins are to function as either analog or digital inputs, the VREF and ANGND pins must provide power. If the voltage applied to the analog input exceeds VREF or ANGND by more than 0.5 volts, current will be driven through Q1 or Q2 into the reference circuitry, decreasing the accuracy of all analog conversions.

The port pin is sampled one state time before the read buffer is enabled. Sampling occurs during phase 1 (while CLKOUT is low) and resolves the value of the pin before it is presented to the internal bus. To ensure that the value is recognized, it must be valid 45 ns before the rising edge of CLKOUT and must remain valid until CLKOUT falls. If the pin value changes during the sam- ple time, the new value may or may not be recorded.

As a digital input, a pin acts as a high-impedance input. However, as an analog input, a pin must provide current for a short time to charge the internal sample capacitor when a conversion begins. This means that if a conversion is taking place on a port pin, its input characteristics change mo- mentarily.

6.3BIDIRECTIONAL PORTS 1 (MH ONLY), 2, 5, AND 7 (MD ONLY)

Although the bidirectional ports are very similar in both circuitry and configuration, port 5 differs from the others in some ways. Port 5, a memory-mapped port, uses a standard CMOS input buffer because of the high speeds required for system control functions. The remaining bidirectional ports use Schmitt-triggered input buffers for improved noise immunity.

NOTE

Ports 3 and 4 are significantly different from the other bidirectional ports. See “Bidirectional Ports 3 and 4 (Address/Data Bus)” on page 6-14 for details on the structure and operation of these ports.

Table 6-4 lists the bidirectional port pins with their special-function signals and associated periph- erals.

6-4