REGISTERS

T2CONTROL

T2CONTROL

Address:

1F7CH

 

Reset State:

00H

The timer 2 control (T2CONTROL) register determines the clock source, counting direction, and count rate for timer 2.

7

CE

UD

M2

M1

 

 

 

 

0

M0

P2

P1

P0

 

 

 

 

Bit

Bit

 

 

 

 

Function

 

Number

Mnemonic

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

CE

Counter Enable

 

 

 

 

 

This bit enables or disables the timer. From reset, the timers are

 

 

disabled and not free running.

 

 

 

 

0

= disables timer

 

 

 

 

 

1

= enables timer

 

 

 

 

 

 

 

 

 

 

6

UD

Up/Down

 

 

 

 

 

 

This bit determines the timer counting direction, in selected modes (see

 

 

mode bits, M2:0).

 

 

 

 

 

0

= count down

 

 

 

 

 

1

= count up

 

 

 

 

 

 

 

 

 

5:3

M2:0

EPA Clock Direction Mode Bits

 

 

 

 

These bits determine the timer clocking source and direction source.

 

 

M2

M1

M0

Clock Source

Direction Source

 

 

0

 

0

0

FXTAL1/4

UD bit (T2CONTROL.6)

 

 

X

 

0

1

reserved

 

 

 

0

 

1

0

reserved

 

 

 

0

 

1

1

reserved

 

 

 

1

 

0

0

timer 1 overflow

UD bit (T2CONTROL.6)

 

 

1

 

1

0

timer 1 overflow

same as timer 1

 

 

1

 

1

1

reserved

 

 

 

 

 

 

2:0

P2:0

EPA Clock Prescaler Bits

 

 

 

 

These bits determine the clock prescaler value.

 

 

 

P2

P1

P0

Prescaler

 

Resolution

 

 

0

 

0

0

divide by 1 (disabled)

250 ns

 

 

0

 

0

1

divide by 2

 

500 ns

 

 

0

 

1

0

divide by 4

 

1 µs

 

 

0

 

1

1

divide by 8

 

2 µs

 

 

1

 

0

0

divide by 16

 

4 µs

 

 

1

 

0

1

divide by 32

 

8 µs

 

 

1

 

1

0

divide by 64

 

16 µs

 

 

1

 

1

1

reserved

 

 

 

 

Resolution at 16 MHz. Use the formula on page 11-6 to calculate the

 

 

 

 

 

 

 

 

resolution at other frequencies.

 

 

 

 

 

 

 

 

 

 

 

C-55

Page 532
Image 532
Intel 8XC196MH, 8XC196MD, 8XC196MC manual T2CONTROL